2009年8月24日星期一
VPBE寄存器描述
1.PINMUX1
22 VCLK Enable VCLK
0 VCLK
1 GIO[68]
21-20 EXTCLK Enable EXTCLK (Video Out pin mux)
0 GIO[69]
1h EXTCLK
2h B2
3h PWM3
19-18 FIELD Enable FIELD (Video Out pin mux)
0 GIO[70]
1h FIELD
2h R2
3h PWM3
17 DCLD Enable DLCD signal output (Video Out pin mux)
0 LCD_OE or BRIGHT (set by LDCOUT.OES)
1 GIO[71]
16 HYSYNC Enable HVSYNC (Video Out pin mux)
0 HVSYNC and VSYNC
1 GIO[73:72]
15-14 COUT_0 Enable COUT[0] (Video Out pin mux)
0 GIO[74]
1h COUT[0]
2h PWM3
13-12 COUT_1 Enable COUT[1] (Video Out pin mux)
0\ GIO[75]
1h COUT[1]
2h PWM3
3h Reserved
11-10 COUT_2 Enable COUT[2] (Video Out pin mux)
0 GIO[76]
1h COUT[2]
2h PWM2
3h RTO3
9-8 COUT_3 Enable COUT[3] (Video Out pin mux)
0 GIO[77]
1h COUT[3]
2h PWM2
3h RTO2
7-6 COUT_4 Enable COUT[4] (Video Out pin mux)
0 GIO[78]
1h COUT[4]
2h PWM2
3h RTO1
5-4 COUT_5 Enable COUT[5] (Video Out pin mux)
0 GIO[79]
1h COUT[5]
2h PWM2
3h RTO0
3-2 COUT_6 Enable COUT[6] (Video Out pin mux)
0 GIO[80]
1h COUT[6]
2h PWM1
3h Reserved
1-0 COUT_7 Enable COUT[7] (Video Out pin mux)
0 GIO[81]
1h COUT[7]
2h PWM0
3h Reserved
3 VPBE Integration
VPBE实则是一个DMA主控器
VPBE不用时可让VPSSCLK.CLKCTRL.VPBE_CLK禁用，但若使用，则应先打开，再进行其它操作
3.1.1.4 VPSS Clock Mux Control Register (VPSS_CLK_CTRL)
6-5 VENC_CLK_SRC 27 MHz input source
0 PLL1 divided down
1 (EXTCRYSTAL2) External crystal 2
2h (EXTCRYSTAL1) External crystal 1
3h Reserved
4 DACCLKEN Video DAC clock enable
0 Disabled
1 Enabled
3 VENCLKEN VPBE/Video encoder clock enable
0 Disabled
1 Enabled
2 PCLK_INV Invert VPFE pixel clock (PCLK)
0 Disable VENC clock mux and CCDC receive normal PCLK
1 Enable VENC clock mux and CCDC receive inverted PCLK
1-0 VPSS_MUXSEL 0-3h VPSS clock selection
0 Use input set by VENC_CLK_SRC (typically 27 MHZ).
1h Reserved
2h EXTCLK mode. Use external VPBE clock input (DAC clock = EXTCLK).
3h PCLK mode. Use PCLK from VPFE (DAC clock = off).
3.1.1.5 MXI2 Oscillator Power Control：USB Physical Control Register (USB_PHY_CTRL)
11 DATAPOL USB PHY data polarity inversion
0 USB PHY data polarity, no inversion
1 USB PHY data polarity inversion
10 - 9 PHYCLKSRC USB PHY input clock source
0 24 MHz directly from crystal
1h 12 MHz (after dividing 36 MHz crystal by 3)
2h {PLLCTRL1.SYSCLK3) backup in case 27 MHz crystal is used.
3h Reserved
8 PHYCLKGD USB PHY power and clock good
0 BAD - PHY power not ramped or PLL not locked
1 GOOD - PHY power is good and PLL is locked
7 SESNDEN Session end comparator enable
0 DISABLE - Comparator disabled
1 ENABLE - Comparator enabled
6 VBDTCTEN VBUS comparator enabled
0 DISABLE - Comparators (except session end) disabled
1 ENABLE - Comparators (except session end) enabled
5 VBUSENS OTG analog block VBUSSENSE output status
0 ABSENT - VBUS not present (<0.5 V)
1 PRESENT - VBUS present (>0.5 V)
4 PHYPLLON USB PHY PLL suspend override
0 Normal PLL operation
1 Override PLL suspend state
3 Reserved Reserved
2 VPSS VPSS oscillator power down controlOSCPDWN
0 VPSS MXI2 powered on
1 VPSS MXI2 power off
1 OTGPDWN USB OTG analog block power down control
0 OTG analog block powered on
1 OTG analog block power off
0 PHYPDWN USB PHY power down control
0 PHY powered on
1 PHY power off
3.1.2 Resets
不要用SyncReset or SwRstDisable states of the PSC
3.3 Video DAC Configuration
在SYSTEM MODULE中VDAC_CONFIG 值，推荐：
· TRESB4R4 = 0x3
· TRESB4R2 = 0x8
· TRESB4R1 = 0x8
· TRIMBITS = 0x34
· PWD_BGZ = 1 (power-up VREF)
· SPEED = 1 (faster)
· PWD_VBUFZ = 1 (power-up video buffer)
· ACCUP_EN = 0 (default 1)
· DINV = 1 (invert)
3.3.1 Video DAC Configuration Register (VDAC CONFIG)
29-26 TRESB4R4 Resistance trimming control bit for VREF
25-22 TRESB4R2 Resistance trimming control bit for VREF
21-18 TRESB4R1 Resistance trimming control bit for VREF
17-11 TRIMBITS PNP transistor trimming control bit for VREF
10 PWD_BGZ Power Down of VREFF
0 power down
1 power Up
9 SPEED Faster operation of VREF transfer
0 Normal
1 Faster
8 TVINT TV cable connect status from DAC
0 Cable connected
1 Cable disconnected
7 PWD_VBUFZ Power down of video buffer
0 Power Down
1 Power UP
6-4 VREFSET VREF setting to vedio buffer
3 ACCUP_EN AC capacitor coupling externally to video buffer
0 Disable the coupling
1 Enable the coupling
2 DINV Data invert from VENC (inside the DAC)
0 No inversion - use only when VDAC is used without VREF and buffer
1 Inversion _ When VDAC is used with VREF and buffer
1 RESERVED Reserved
0 RESERVED Reserved
4.3 Master/Slave Mode Interface
Master Mode Configuration Registers
Acronym Register
HSPLS Horizontal sync pulse width
VSPLS Vertical sync pulse width
HINT Horizontal interval
HSTART Horizontal valid data start position
HVALID Horizontal data valid range
VINT Vertical interval
VSTART Vertical valid data start position
VVALID Vertical data valid range
HSDLY Horizontal sync delay
VSDLY Vertical sync delay
4.4.1 Video Window Constraints
1.用VIDEO WINDOW0作HD显示
2.当VIDEO WINDOW0作HD显示时，VIDEO WINDOW1禁用
4.4.2.1 DDR Addresses
OSD SDRAM Address Registers
SDRAM Address Register Window
VIDWIN0ADL Video window 0 address (low 16 bits)
VIDWIN1ADL Video window 1 address (low 16 bits)
VIDWINADH Video window addresses (upper bits)
OSDWIN0ADL OSD bitmap window 0 address (low 16 bits)
OSDWIN1ADL OSD bitmap window 1/attribute window address (low 16 bits)
OSDWINADH OSD bitmap window addresses (upper bits)
4.4.2.2 DDR Offsets
显示区域的每行尺寸偏移，可行显示一个影像的子集（部分）
OSD SDRAM Offset Registers
SDRAM Address Register Window
VIDWIN0OFST Video Window 0 SDRAM offset register
VIDWIN1OFST Video Window 1 SDRAM offset register
OSDWIN0OFST OSD Bitmap Window 0 SDRAM offset register
OSDWIN1OFST OSD Bitmap Window 1/Attribute Window SDRAM offset register
4.4.2.3 Window Positioning
1. BASEP_X and BASEP_Y 以HD，VD前沿为参考点
2. 当VENC为INTERFACE （交错模式），则YP，YL的定义为每FIELD的行数；若为PROGRESSIVE则定义为第FRAME的行数。
OSD Window Positioning Registers
Window Positioning Registers Window
VIDWIN0XP Video Window 0 start position and size registers
VIDWIN0YP
VIDWIN0XL 行像素
VIDWIN0YL 行数
====================================================================================
VIDWIN1XP Video Window 1 start position and size registers
VIDWIN1YP
VIDWIN1XL
VIDWIN1YL
======================================================================================
OSDWIN0XP OSD Bitmap Window 0 start position and size registers
OSDWIN0YP
OSDWIN0XL
OSDWIN0YL
OSDWIN1XP OSD Bitmap Window 1/Attribute Window start position and size registers
OSDWIN1YP
OSDWIN1XL
OSDWIN1YL
======================================================================================
CURXP Hardware cursor start position and size registers
CURYP
CURXL
CURYL
4.4.2.4 Window Mode – Field/Frame
OSD Field/Frame Mode Registers
Register.Field Description
VIDWINMD.VFF0 Video Window 0 Field/Frame specification
VIDWINMD.VFF1 Video Window 1 Field/Frame specification
OSDWIN0MD.OFF0 OSD Bitmap Window 0 Field/Frame specification
OSDWIN1MD.OFF1 OSD Bitmap Window 1 Field/Frame specification
OSDATRMD.OFFA OSD Attribute Window Field/Frame specification
(same address/offset as for OSD Bitmap Window 1)
4.4.2.4.1 Frame Mode
此时在DDR中的数据是以PROGRESSIVE模式存放。
此时VENC只能为INTERLACE，WINDOW HEIGHT=LINES/FIELD=1/2 DISPLAY HEIGHT，以2 X OFFSET 增加地址
4.4.2.4.2 Field Mode
1.VENC为INTERLACE模式，WINDOW HEIGHT=LINES/FIELD=1/2 DISPLAY HEIGHT，后FIELD重读DDR中前FIELD处地址空间数据
2.VENC为PROGRESSIVE模式，WINDOW HEIGHT=LINES/FRAME=FULL DISPLAY HEIGHT
4.4.2.5 Window Scaling
有两种方式放大：
一种是以像素COPY方，x2 and x4
另一种是以线性插值方式，x9/8 （640转720）and x3/2 （640转960）in horizontal direction and x6/5 （480转576）in vertical direction.
4.4.2.5.1 Window Zooming
在DDR中选取要放大的数据区域，在设置屏幕显示位置
OSD Window Zoom Registers
Register. Field Description
VIDWINMD.VHZ0 Video Window 0 Horizontal Zoom
VIDWINMD.VVZ0 Video Window 0 Vertical Zoom
VIDWINMD.VHZ1 Video Window 1 Horizontal Zoom
VIDWINMD.VVZ1 Video Window 1 Vertical Zoom
OSDWIN0MD.OHZ0 Bitmap Window 0 Horizontal Zoom
OSDWIN0MD.OVZ0 Bitmap Window 0 Vertical Zoom
OSDWIN1MD.OHZ1 Bitmap Window 1 Horizontal Zoom
OSDWIN1MD.OVZ1 Bitmap Window 1 Vertical Zoom
4.4.2.5.2 Window Scaling – Square Pixels for NTSC/PAL Analog Output or Display Matching
Normal OSD Window Expansion Registers
Register Field Description
MODE.VHRSZ Video Window Horizontal 9/8 Expansion
MODE.VVRSZ Video Window Vertical 6/5 Expansion
MODE.V0EFC Video Window 0 smoothing filter enable (with MODE.EF)
MODE.V1EFC Video Window 1 smoothing filter enable (with MODE.EF)
MODE.EF Video Window smoothing filter (maximum line width is 720)
MODE.OHRSZ Video Window Horizontal 9/8 Expansion
MODE.OVRSZ Video Window Vertical 6/5 Expansion
Extended OSD Window Expansion Registers
Register.Field Description
EXTMODE.EXPMDSEL Sets filtering mode before expansion
EXTMODE.SCRNHEXP Global H expansion on all windows
EXTMODE.SCRNVEXP Global V expansion for all windows
EXTMODE.OSDHRSZ15 Bitmap window 1.5x expansion if normal filtering done
EXTMODE.VIDHRAZ15 Video window 1.5x expansion if normal filtering done
4.4.2.5.3 Zoom and Expansion Filter Usage
vertical expansion filter 优先权比 vertical zoom filter高
4.4.2.5.4 Window Positioning Limits for When Using Horizontal Expansion
当水平Expansion时，同类型窗口有位置限制，不能随便设置
4.4.2.5.6 Vertical Boundary Processing
4.4.2.6 OSD Background Color
OSD Background Color Registers
Register. Field Description
MODE.BCLUT Selects the color lookup table to be used (ROM or RAM). Note that there
are two ROM tables and the selection for the other windows also applies
here (MISCCTL.RSEL).
MODE.CABG Background color. 8-bit offset into color lookup table.
Pixel Arrangement in the Display（SDRAM）
Left, Top
P0 P1 P2 P3 P4 P5 P6 P7 ...
4.4.3.2 Expansion and Anti-Flicker Filter for Video Window
Expansion and Anti-Flicker Filter for Video Window
Register.Field Description
MODE.EF Expansion filter enable. Only use when EXTMODE.EXPMDSEL = 0
WIDWINMD.VFINV Inverts application of the two sets of expansion filter
coefficients betweenfield 0 and field 1.
WIDWINMD.VnEFC Enables different anti-flicker coefficients for each field
EXTMODE.EXPMDSEL Extended mode expansion filtering mode select
EXTMODE.ZMFILVnVEN Extended mode - video window n vertical zoom filter type (x6/5)
EXTMODE.ZMFILVnHEN Extended mode - video window n horizontal zoom filter type
EXTMODE.EXPFILHEN Extended mode - video window horizontal expansion filter enable (x9/8, x1/5)
EXTMODE.EXPFILVEN Extended mode - video window vertical expansion filter enable (x6/5)
4.4.3.2.2 Video Window Filtering - Vertical Direction
4.4.3.2.2.1 Vertical x1 Anti-Flicker (Expansion) Filter (Field Rate Conversion)
（FIELD-BASED IMAGE TO DISPLAY）
Vertical x1 Anti-Flicker Filter Control Registers
Register Field Value
WIDWINMD.FSINV 1
or
WIDWINMD.VFINV
=============================================================================================
WIDWINMD.VnEFC 0 or 1
Operation of Vertical x1 Anti-Flicker Filter Control Registers
Invert bit (VIDWINMD.VFINF or MODE.FSINV) 0 1
Expand Filter (V)
Coefficient bit (VIDWINMD.VnEFC) Different (due to same field source)
ON FID = 0 1 FID = 0 2
FID = 1 2 FID = 1 1
OFF FID = 0 1 FID = 0 1
FID = 1 1 FID = 1 1
4.4.3.2.2.2 Vertical x1 Anti-Flicker (Expansion) Filter (Without Field Rate Conversion):the filtering function is not applied(不用FILER）
FIELD-BASED IMAGE TO DISPLAY
Operation of Vertical x1 Anti-Flicker Filter Control Registers
Invert bit (VIDWINMD.VFINF or MODE.FSINV) 0 1
Expand Filter (V)
Coefficient Bit (VIDWINMD.VnEFC) Same (due to different field source)
ON FID = 0 1 FID = 0 1
FID = 1 1 FID = 1 1
OFF FID = 0 1 FID = 0 1
FID = 1 1 FID = 1 1
4.4.3.2.2.3 Vertical x1 Anti-Flicker (Expansion) Filter (Frame Source Data Case)
FRAME-BASED IMAGE
the filtering function is not applied（FILER功能不用）
Operation of Vertical x1 Anti-Flicker Filter for Frame Mode
Invert bit (VIDWINMD.VFINF or MODE.FSINV) 0 1 Expand Filter (V)
Coefficient bit (VIDWINMD.VnEFC) Different (due to same field source)
ON FID = 0 1 FID = 0 2
FID = 1 2 FID = 1 1
OFF FID = 0 1 FID = 0 2
FID = 1 2 FID = 1 1
4.4.4 Bitmap Windows
4.4.4.1 Color LookUp Tables
有三个LUT，两个ROM的，一个RAM的，RAM可编程，编程顺序如下：
1. 等 MISCCTL.CPBSY 清 0.
2. 写Y 及 Cb 到 CLUTRAMYCB .
3. 写Cr 及 CLUT address 到 CLUTRAMCR register. The address 为CLUT RAM中Y,CB,CR的偏移值
4. 重复以上.
OSD Color Look-Up Table Registers
Register.Field Description
ROM color look-up table MISCCTL.RSEL Selects the ROM color look-p table to use for
all options that selection select the
ROM table (0=DM270, 1=DM320)
Background color selection MODE.BCLUT Background CLUT selection (ROM or RAM)
MODE.CABG Background CLUT selection (offset into 256- bit table)
Cursor CLUT selection RECTCUR.CLUTSR Cursor CLUT selection (ROM or RAM)
RECTCUR.RCAD Rectangular Cursor color address within
CLUT(offset into256-bit table)
Bitmap window CLUT OSDWIN0MD.CLUTS0 Window 0 CLUT selection (ROM or RAM)
selections OSDWIN1MD.CLUTS1 Window 1 CLUT selection (ROM or RAM)
RAM CLUT Setup/Write CLUTRAMYCB.Y CLUTRAM Y (luma) value
CLUTRAMYCB.CB CLUTRAM CB (chroma) value
CLUTRAMCR.CR CLUTRAM CR (chroma) value
CLUTRAMCR.CADDR CLUTRAM address offset (writes all values)
MISCCTL.CPBUSY Indicates if busy when writing to CLUT RAM
CLUT Mapping for 1-Bit, 2-Bit, or 4-Bit Bitmaps
Register.Field Color Corresponding to Bitmap Value
(n = 0 or 1 for OSD Bitmap
Window 0 or 1, respectively) 4-Bit Bitmap 2-Bit Bitmap 1-Bit Bitmap
WnBMP01.PAL00 0 0 0
WnBMP01.PAL01 1 - -
WnBMP23.PAL02 2 - -
WnBMP23.PAL03 3 - -
WnBMP45.PAL04 4 - -
WnBMP45.PAL05 5 1 -
WnBMP67.PAL06 6 - -
WnBMP67.PAL07 7 - -
WnBMP89.PAL08 8 - -
WnBMP89.PAL09 9 - -
WnBMPAB.PAL10 10 2 -
WnBMPAB.PAL11 11 - -
WnBMPCD.PAL12 12 - -
WnBMPCD.PAL13 13 - -
WnBMPEF.PAL14 14 - -
WnBMPEF.PAL15 15 3 1
22 VCLK Enable VCLK
0 VCLK
1 GIO[68]
21-20 EXTCLK Enable EXTCLK (Video Out pin mux)
0 GIO[69]
1h EXTCLK
2h B2
3h PWM3
19-18 FIELD Enable FIELD (Video Out pin mux)
0 GIO[70]
1h FIELD
2h R2
3h PWM3
17 DCLD Enable DLCD signal output (Video Out pin mux)
0 LCD_OE or BRIGHT (set by LDCOUT.OES)
1 GIO[71]
16 HYSYNC Enable HVSYNC (Video Out pin mux)
0 HVSYNC and VSYNC
1 GIO[73:72]
15-14 COUT_0 Enable COUT[0] (Video Out pin mux)
0 GIO[74]
1h COUT[0]
2h PWM3
13-12 COUT_1 Enable COUT[1] (Video Out pin mux)
0\ GIO[75]
1h COUT[1]
2h PWM3
3h Reserved
11-10 COUT_2 Enable COUT[2] (Video Out pin mux)
0 GIO[76]
1h COUT[2]
2h PWM2
3h RTO3
9-8 COUT_3 Enable COUT[3] (Video Out pin mux)
0 GIO[77]
1h COUT[3]
2h PWM2
3h RTO2
7-6 COUT_4 Enable COUT[4] (Video Out pin mux)
0 GIO[78]
1h COUT[4]
2h PWM2
3h RTO1
5-4 COUT_5 Enable COUT[5] (Video Out pin mux)
0 GIO[79]
1h COUT[5]
2h PWM2
3h RTO0
3-2 COUT_6 Enable COUT[6] (Video Out pin mux)
0 GIO[80]
1h COUT[6]
2h PWM1
3h Reserved
1-0 COUT_7 Enable COUT[7] (Video Out pin mux)
0 GIO[81]
1h COUT[7]
2h PWM0
3h Reserved
3 VPBE Integration
VPBE实则是一个DMA主控器
VPBE不用时可让VPSSCLK.CLKCTRL.VPBE_CLK禁用，但若使用，则应先打开，再进行其它操作
3.1.1.4 VPSS Clock Mux Control Register (VPSS_CLK_CTRL)
6-5 VENC_CLK_SRC 27 MHz input source
0 PLL1 divided down
1 (EXTCRYSTAL2) External crystal 2
2h (EXTCRYSTAL1) External crystal 1
3h Reserved
4 DACCLKEN Video DAC clock enable
0 Disabled
1 Enabled
3 VENCLKEN VPBE/Video encoder clock enable
0 Disabled
1 Enabled
2 PCLK_INV Invert VPFE pixel clock (PCLK)
0 Disable VENC clock mux and CCDC receive normal PCLK
1 Enable VENC clock mux and CCDC receive inverted PCLK
1-0 VPSS_MUXSEL 0-3h VPSS clock selection
0 Use input set by VENC_CLK_SRC (typically 27 MHZ).
1h Reserved
2h EXTCLK mode. Use external VPBE clock input (DAC clock = EXTCLK).
3h PCLK mode. Use PCLK from VPFE (DAC clock = off).
3.1.1.5 MXI2 Oscillator Power Control：USB Physical Control Register (USB_PHY_CTRL)
11 DATAPOL USB PHY data polarity inversion
0 USB PHY data polarity, no inversion
1 USB PHY data polarity inversion
10 - 9 PHYCLKSRC USB PHY input clock source
0 24 MHz directly from crystal
1h 12 MHz (after dividing 36 MHz crystal by 3)
2h {PLLCTRL1.SYSCLK3) backup in case 27 MHz crystal is used.
3h Reserved
8 PHYCLKGD USB PHY power and clock good
0 BAD - PHY power not ramped or PLL not locked
1 GOOD - PHY power is good and PLL is locked
7 SESNDEN Session end comparator enable
0 DISABLE - Comparator disabled
1 ENABLE - Comparator enabled
6 VBDTCTEN VBUS comparator enabled
0 DISABLE - Comparators (except session end) disabled
1 ENABLE - Comparators (except session end) enabled
5 VBUSENS OTG analog block VBUSSENSE output status
0 ABSENT - VBUS not present (<0.5 V)
1 PRESENT - VBUS present (>0.5 V)
4 PHYPLLON USB PHY PLL suspend override
0 Normal PLL operation
1 Override PLL suspend state
3 Reserved Reserved
2 VPSS VPSS oscillator power down controlOSCPDWN
0 VPSS MXI2 powered on
1 VPSS MXI2 power off
1 OTGPDWN USB OTG analog block power down control
0 OTG analog block powered on
1 OTG analog block power off
0 PHYPDWN USB PHY power down control
0 PHY powered on
1 PHY power off
3.1.2 Resets
不要用SyncReset or SwRstDisable states of the PSC
3.3 Video DAC Configuration
在SYSTEM MODULE中VDAC_CONFIG 值，推荐：
· TRESB4R4 = 0x3
· TRESB4R2 = 0x8
· TRESB4R1 = 0x8
· TRIMBITS = 0x34
· PWD_BGZ = 1 (power-up VREF)
· SPEED = 1 (faster)
· PWD_VBUFZ = 1 (power-up video buffer)
· ACCUP_EN = 0 (default 1)
· DINV = 1 (invert)
3.3.1 Video DAC Configuration Register (VDAC CONFIG)
29-26 TRESB4R4 Resistance trimming control bit for VREF
25-22 TRESB4R2 Resistance trimming control bit for VREF
21-18 TRESB4R1 Resistance trimming control bit for VREF
17-11 TRIMBITS PNP transistor trimming control bit for VREF
10 PWD_BGZ Power Down of VREFF
0 power down
1 power Up
9 SPEED Faster operation of VREF transfer
0 Normal
1 Faster
8 TVINT TV cable connect status from DAC
0 Cable connected
1 Cable disconnected
7 PWD_VBUFZ Power down of video buffer
0 Power Down
1 Power UP
6-4 VREFSET VREF setting to vedio buffer
3 ACCUP_EN AC capacitor coupling externally to video buffer
0 Disable the coupling
1 Enable the coupling
2 DINV Data invert from VENC (inside the DAC)
0 No inversion - use only when VDAC is used without VREF and buffer
1 Inversion _ When VDAC is used with VREF and buffer
1 RESERVED Reserved
0 RESERVED Reserved
4.3 Master/Slave Mode Interface
Master Mode Configuration Registers
Acronym Register
HSPLS Horizontal sync pulse width
VSPLS Vertical sync pulse width
HINT Horizontal interval
HSTART Horizontal valid data start position
HVALID Horizontal data valid range
VINT Vertical interval
VSTART Vertical valid data start position
VVALID Vertical data valid range
HSDLY Horizontal sync delay
VSDLY Vertical sync delay
4.4.1 Video Window Constraints
1.用VIDEO WINDOW0作HD显示
2.当VIDEO WINDOW0作HD显示时，VIDEO WINDOW1禁用
4.4.2.1 DDR Addresses
OSD SDRAM Address Registers
SDRAM Address Register Window
VIDWIN0ADL Video window 0 address (low 16 bits)
VIDWIN1ADL Video window 1 address (low 16 bits)
VIDWINADH Video window addresses (upper bits)
OSDWIN0ADL OSD bitmap window 0 address (low 16 bits)
OSDWIN1ADL OSD bitmap window 1/attribute window address (low 16 bits)
OSDWINADH OSD bitmap window addresses (upper bits)
4.4.2.2 DDR Offsets
显示区域的每行尺寸偏移，可行显示一个影像的子集（部分）
OSD SDRAM Offset Registers
SDRAM Address Register Window
VIDWIN0OFST Video Window 0 SDRAM offset register
VIDWIN1OFST Video Window 1 SDRAM offset register
OSDWIN0OFST OSD Bitmap Window 0 SDRAM offset register
OSDWIN1OFST OSD Bitmap Window 1/Attribute Window SDRAM offset register
4.4.2.3 Window Positioning
1. BASEP_X and BASEP_Y 以HD，VD前沿为参考点
2. 当VENC为INTERFACE （交错模式），则YP，YL的定义为每FIELD的行数；若为PROGRESSIVE则定义为第FRAME的行数。
OSD Window Positioning Registers
Window Positioning Registers Window
VIDWIN0XP Video Window 0 start position and size registers
VIDWIN0YP
VIDWIN0XL 行像素
VIDWIN0YL 行数
====================================================================================
VIDWIN1XP Video Window 1 start position and size registers
VIDWIN1YP
VIDWIN1XL
VIDWIN1YL
======================================================================================
OSDWIN0XP OSD Bitmap Window 0 start position and size registers
OSDWIN0YP
OSDWIN0XL
OSDWIN0YL
OSDWIN1XP OSD Bitmap Window 1/Attribute Window start position and size registers
OSDWIN1YP
OSDWIN1XL
OSDWIN1YL
======================================================================================
CURXP Hardware cursor start position and size registers
CURYP
CURXL
CURYL
4.4.2.4 Window Mode – Field/Frame
OSD Field/Frame Mode Registers
Register.Field Description
VIDWINMD.VFF0 Video Window 0 Field/Frame specification
VIDWINMD.VFF1 Video Window 1 Field/Frame specification
OSDWIN0MD.OFF0 OSD Bitmap Window 0 Field/Frame specification
OSDWIN1MD.OFF1 OSD Bitmap Window 1 Field/Frame specification
OSDATRMD.OFFA OSD Attribute Window Field/Frame specification
(same address/offset as for OSD Bitmap Window 1)
4.4.2.4.1 Frame Mode
此时在DDR中的数据是以PROGRESSIVE模式存放。
此时VENC只能为INTERLACE，WINDOW HEIGHT=LINES/FIELD=1/2 DISPLAY HEIGHT，以2 X OFFSET 增加地址
4.4.2.4.2 Field Mode
1.VENC为INTERLACE模式，WINDOW HEIGHT=LINES/FIELD=1/2 DISPLAY HEIGHT，后FIELD重读DDR中前FIELD处地址空间数据
2.VENC为PROGRESSIVE模式，WINDOW HEIGHT=LINES/FRAME=FULL DISPLAY HEIGHT
4.4.2.5 Window Scaling
有两种方式放大：
一种是以像素COPY方，x2 and x4
另一种是以线性插值方式，x9/8 （640转720）and x3/2 （640转960）in horizontal direction and x6/5 （480转576）in vertical direction.
4.4.2.5.1 Window Zooming
在DDR中选取要放大的数据区域，在设置屏幕显示位置
OSD Window Zoom Registers
Register. Field Description
VIDWINMD.VHZ0 Video Window 0 Horizontal Zoom
VIDWINMD.VVZ0 Video Window 0 Vertical Zoom
VIDWINMD.VHZ1 Video Window 1 Horizontal Zoom
VIDWINMD.VVZ1 Video Window 1 Vertical Zoom
OSDWIN0MD.OHZ0 Bitmap Window 0 Horizontal Zoom
OSDWIN0MD.OVZ0 Bitmap Window 0 Vertical Zoom
OSDWIN1MD.OHZ1 Bitmap Window 1 Horizontal Zoom
OSDWIN1MD.OVZ1 Bitmap Window 1 Vertical Zoom
4.4.2.5.2 Window Scaling – Square Pixels for NTSC/PAL Analog Output or Display Matching
Normal OSD Window Expansion Registers
Register Field Description
MODE.VHRSZ Video Window Horizontal 9/8 Expansion
MODE.VVRSZ Video Window Vertical 6/5 Expansion
MODE.V0EFC Video Window 0 smoothing filter enable (with MODE.EF)
MODE.V1EFC Video Window 1 smoothing filter enable (with MODE.EF)
MODE.EF Video Window smoothing filter (maximum line width is 720)
MODE.OHRSZ Video Window Horizontal 9/8 Expansion
MODE.OVRSZ Video Window Vertical 6/5 Expansion
Extended OSD Window Expansion Registers
Register.Field Description
EXTMODE.EXPMDSEL Sets filtering mode before expansion
EXTMODE.SCRNHEXP Global H expansion on all windows
EXTMODE.SCRNVEXP Global V expansion for all windows
EXTMODE.OSDHRSZ15 Bitmap window 1.5x expansion if normal filtering done
EXTMODE.VIDHRAZ15 Video window 1.5x expansion if normal filtering done
4.4.2.5.3 Zoom and Expansion Filter Usage
vertical expansion filter 优先权比 vertical zoom filter高
4.4.2.5.4 Window Positioning Limits for When Using Horizontal Expansion
当水平Expansion时，同类型窗口有位置限制，不能随便设置
4.4.2.5.6 Vertical Boundary Processing
4.4.2.6 OSD Background Color
OSD Background Color Registers
Register. Field Description
MODE.BCLUT Selects the color lookup table to be used (ROM or RAM). Note that there
are two ROM tables and the selection for the other windows also applies
here (MISCCTL.RSEL).
MODE.CABG Background color. 8-bit offset into color lookup table.
Pixel Arrangement in the Display（SDRAM）
Left, Top
P0 P1 P2 P3 P4 P5 P6 P7 ...
4.4.3.2 Expansion and Anti-Flicker Filter for Video Window
Expansion and Anti-Flicker Filter for Video Window
Register.Field Description
MODE.EF Expansion filter enable. Only use when EXTMODE.EXPMDSEL = 0
WIDWINMD.VFINV Inverts application of the two sets of expansion filter
coefficients betweenfield 0 and field 1.
WIDWINMD.VnEFC Enables different anti-flicker coefficients for each field
EXTMODE.EXPMDSEL Extended mode expansion filtering mode select
EXTMODE.ZMFILVnVEN Extended mode - video window n vertical zoom filter type (x6/5)
EXTMODE.ZMFILVnHEN Extended mode - video window n horizontal zoom filter type
EXTMODE.EXPFILHEN Extended mode - video window horizontal expansion filter enable (x9/8, x1/5)
EXTMODE.EXPFILVEN Extended mode - video window vertical expansion filter enable (x6/5)
4.4.3.2.2 Video Window Filtering - Vertical Direction
4.4.3.2.2.1 Vertical x1 Anti-Flicker (Expansion) Filter (Field Rate Conversion)
（FIELD-BASED IMAGE TO DISPLAY）
Vertical x1 Anti-Flicker Filter Control Registers
Register Field Value
WIDWINMD.FSINV 1
or
WIDWINMD.VFINV
=============================================================================================
WIDWINMD.VnEFC 0 or 1
Operation of Vertical x1 Anti-Flicker Filter Control Registers
Invert bit (VIDWINMD.VFINF or MODE.FSINV) 0 1
Expand Filter (V)
Coefficient bit (VIDWINMD.VnEFC) Different (due to same field source)
ON FID = 0 1 FID = 0 2
FID = 1 2 FID = 1 1
OFF FID = 0 1 FID = 0 1
FID = 1 1 FID = 1 1
4.4.3.2.2.2 Vertical x1 Anti-Flicker (Expansion) Filter (Without Field Rate Conversion):the filtering function is not applied(不用FILER）
FIELD-BASED IMAGE TO DISPLAY
Operation of Vertical x1 Anti-Flicker Filter Control Registers
Invert bit (VIDWINMD.VFINF or MODE.FSINV) 0 1
Expand Filter (V)
Coefficient Bit (VIDWINMD.VnEFC) Same (due to different field source)
ON FID = 0 1 FID = 0 1
FID = 1 1 FID = 1 1
OFF FID = 0 1 FID = 0 1
FID = 1 1 FID = 1 1
4.4.3.2.2.3 Vertical x1 Anti-Flicker (Expansion) Filter (Frame Source Data Case)
FRAME-BASED IMAGE
the filtering function is not applied（FILER功能不用）
Operation of Vertical x1 Anti-Flicker Filter for Frame Mode
Invert bit (VIDWINMD.VFINF or MODE.FSINV) 0 1 Expand Filter (V)
Coefficient bit (VIDWINMD.VnEFC) Different (due to same field source)
ON FID = 0 1 FID = 0 2
FID = 1 2 FID = 1 1
OFF FID = 0 1 FID = 0 2
FID = 1 2 FID = 1 1
4.4.4 Bitmap Windows
4.4.4.1 Color LookUp Tables
有三个LUT，两个ROM的，一个RAM的，RAM可编程，编程顺序如下：
1. 等 MISCCTL.CPBSY 清 0.
2. 写Y 及 Cb 到 CLUTRAMYCB .
3. 写Cr 及 CLUT address 到 CLUTRAMCR register. The address 为CLUT RAM中Y,CB,CR的偏移值
4. 重复以上.
OSD Color Look-Up Table Registers
Register.Field Description
ROM color look-up table MISCCTL.RSEL Selects the ROM color look-p table to use for
all options that selection select the
ROM table (0=DM270, 1=DM320)
Background color selection MODE.BCLUT Background CLUT selection (ROM or RAM)
MODE.CABG Background CLUT selection (offset into 256- bit table)
Cursor CLUT selection RECTCUR.CLUTSR Cursor CLUT selection (ROM or RAM)
RECTCUR.RCAD Rectangular Cursor color address within
CLUT(offset into256-bit table)
Bitmap window CLUT OSDWIN0MD.CLUTS0 Window 0 CLUT selection (ROM or RAM)
selections OSDWIN1MD.CLUTS1 Window 1 CLUT selection (ROM or RAM)
RAM CLUT Setup/Write CLUTRAMYCB.Y CLUTRAM Y (luma) value
CLUTRAMYCB.CB CLUTRAM CB (chroma) value
CLUTRAMCR.CR CLUTRAM CR (chroma) value
CLUTRAMCR.CADDR CLUTRAM address offset (writes all values)
MISCCTL.CPBUSY Indicates if busy when writing to CLUT RAM
CLUT Mapping for 1-Bit, 2-Bit, or 4-Bit Bitmaps
Register.Field Color Corresponding to Bitmap Value
(n = 0 or 1 for OSD Bitmap
Window 0 or 1, respectively) 4-Bit Bitmap 2-Bit Bitmap 1-Bit Bitmap
WnBMP01.PAL00 0 0 0
WnBMP01.PAL01 1 - -
WnBMP23.PAL02 2 - -
WnBMP23.PAL03 3 - -
WnBMP45.PAL04 4 - -
WnBMP45.PAL05 5 1 -
WnBMP67.PAL06 6 - -
WnBMP67.PAL07 7 - -
WnBMP89.PAL08 8 - -
WnBMP89.PAL09 9 - -
WnBMPAB.PAL10 10 2 -
WnBMPAB.PAL11 11 - -
WnBMPCD.PAL12 12 - -
WnBMPCD.PAL13 13 - -
WnBMPEF.PAL14 14 - -
WnBMPEF.PAL15 15 3 1
4.4.4.3 Bitmap Window Blending and Transparency
Bitmap Transparency and Blending Settings
Transparency Blending Factor
OSDWINnMD.TEn OSDWINnMD.BLNDn OSD Window Contribution Video Contribution
OFF 0 0 1
1 1/8 7/8
2 2/8 6/8
3 3/8 5/8
4 4/8 4/8
5 5/8 3/8
6 6/8 2/8
7 1 0
ON If pixel value is equal to 0:
0 0 1
1 1/8 7/8
2 2/8 6/8
3 3/8 5/8
4 4/8 4/8
5 5/8 3/8
6 6/8 2/8
7 1 0
If pixel value is not equal to 0:
X 1 0
Bitmap Transparency and Blending Settings
Transparency Blending Factor
OSDWINnMD.TEn OSDWINnMD.BLNDn OSD Window Contribution Video Contribution
OFF 0 0 1
1 1/8 7/8
2 2/8 6/8
3 3/8 5/8
4 4/8 4/8
5 5/8 3/8
6 6/8 2/8
7 1 0
ON If pixel value is equal to 0:
0 0 1
1 1/8 7/8
2 2/8 6/8
3 3/8 5/8
4 4/8 4/8
5 5/8 3/8
6 6/8 2/8
7 1 0
If pixel value is not equal to 0:
X 1 0
华盛顿邮报诗歌比赛
华盛顿邮报搞了一个比赛，要求写两行押韵的诗，第一行能多浪漫就多浪漫，第二行能多不浪漫就多不浪漫，以下是一些入选作品
==========================================
My darling, my lover, my beautiful wife:
Marrying you has screwed up my life
我的心肝，我的挚爱，我美丽的贤妻，
我这辈子就毁在你手里。
==========================================
My darling, my lover, my beautiful wife:
Marrying you has screwed up my life
我的心肝，我的挚爱，我美丽的贤妻，
我这辈子就毁在你手里。
I see your face when I am dreaming.
That's why I always wake up screaming.
你的容颜依稀入梦境，
于是我在尖叫中惊醒。
Kind, intelligent, loving and hot;
This describes everything you are not.
善良、聪慧、多情而性感，
可惜这些你一条都不占。
Love may be beautiful, love may be bliss,
But I only slept with you 'cause I was pissed.
爱是上天赐福，爱情多么美好，
可我与你同眠只是因为喝高。
I thought that I could love no other
-- that is until I met your brother.
曾以为一生只爱你一个
直到遇见你的二表哥。
Roses are red, violets are blue, sugar is sweet, and so are you.
But the roses are wilting, the violets are dead,the sugar bowl's empty and
so is your head.
娇艳的紫罗兰，鲜红的玫瑰，甜蜜的糖，就像你一样美。
但紫罗兰会凋谢，玫瑰会枯黄，糖碗空空如也，和你的脑袋一样。
I want to feel your sweet embrace;
But don't take that paper bag off your face.
我渴望你温柔的拥抱，
但别把你脸上的面具摘掉。
I love your smile, your face, and your eyes
Damn, I'm good at telling lies!
我爱你的明眸，你的脸庞，你的微笑，
妈的，我真是说谎不打草稿！
My love, you take my breath away.
What have you stepped in to smell this way?
爱人啊，你简直让我窒息，
你在哪沾上的一身臭气？
My feelings for you no words can tell,
Except for maybe "Go to hell."
我对你的深情无法付诸言语，
除了一句"滚一边去"！
What inspired this amorous rhyme?
Two parts vodka, one part lime.
是什么激发了我多情的诗篇？
伏特加两杯，酸柠檬一片。
VPFE寄存器描述
寄存器描述:
一.CCDC
1.Synchronization Enable Register (SYNCEN)
0:VDHDEN
1:WEN
2.MODESET
15:FLDSTAT 0:ODD FIELD 1:EVEN FIELD
14:LPF 3-tap Low-Pass (anti-aliasing) filter for ccd data 0:off 1:on
13-12:INPMOD INPUT MODE 0:CCD RAW DATA 1:YCBCR 16BIT 2:YCBCR 8BIT
11:PACK8 0:NORMAL 16BIT TO SDRAM 1:PACK8 BIT TO SDRAM
10-8:DATASFT 0:NO SHIFT 1-6:SHIFT 1-6BIT
7:FLDMODE 0:NON-INTERFACED 1：INTERFACED （若EXWEN =1，则需为0）
6:DATAPOL 0:NORMAL 1:ONE'S CONPLEMENT
5:EXWEN 0:不用外部WEN 1:用外部VD/HD作为写SDRAM的信号
4:FLDPOL 0:POSITIVE 1:NEGATIVE
3:HDPOL 意思同上
2:VDPOL 意思同上
0:VDHDOUT 0:VD,HD INPUT 1:VD,HD OUTPUT
3. Horizontal Size Register (HSIZE)
12:ADR_UPDT SDRAM 地址更新方式0:自动增加 1:自动减少
11-0:LNOFST SDRAM中行尺寸,32BYTE为单位即16或32PIXELS
4.SDRAM Line Offset Register (SDOFST)
14：FIINV 0：NON INVERSE 1：INVERSE
13-12：FOFST Line offset value of odd field (FID = 1) 0-3：+1 - +4
11-9：LOFST0 Line offset values of even line and even field (FID = 0) 0-7：+1 - -4
8-6：LOFST1 Line offset values of odd line and even field (FID = 0) 同上
5-3：LOFST2 Line offset values of even line and odd field (FID = 1) 同上
2-0：LOFST3 Line offset values of odd line and odd field (FID = 1)同上
5.SDRAM Address - High Register (STADRH)
6.SDRAM Address - LOW Register (STADRL)
7.CCD Color Pattern Register (COLPTN)
8. CCD Gain Adjustment - R/Ye Register (RYEGAIN)
CCD Gain Adjustment - Gr/Cy Register (GRCYGAIN)
CCD Gain Adjustment - Gb/G Register (GBGGAIN)
CCD Gain Adjustment - B/Mg Register (BMGGAIN)
CCD Offset Adjustment Register (OFFSET)
9.Output Clipping Value Register (OUTCLIP)
10.VD Interrupt #0 Register (VDINT0) 中断设定行数
11. VD Interrupt #1 Register (VDINT1)
12. Gamma Correction Settings Register (GAMMAWD)
11-10:MFIL1 Median filter mode for IPIPE 0:no filer 1:average filer 2:median filer
9-8: MFIL1 Median Filter for SDRAM capture.值同上
5：CFAP CFA Pattern. 0：Mosaic 1：Stripe
4-2：GWDI Gamma Width Input (For A-LAW table & H3A port)
0：BITS 13-4 1：12-3 2：11-2 3：10-1 4：9-0
0：CCDTBL Apply Gamma (A-LAW) to CCDC data saved to SDRAM 0：DISABLE 1：ENABLE
13. REC656 Control Register (REC656IF)
1: ECCFVH FVH error correction enable 0:DISABLE 1:ENABLE
0: R656ON REC656 interface enable 0:DISABLE 1:ENABLE
14. CCD Configuration Register (CCDCFG)
15:VDLC Enable synchronizing function regs on VSYNC. 0:Latched on VSYNC. 1:NO LATCHED
13:MSBINVI MSB of Chroma input signal stored to SDRAM inverted.0:NORMAL 1:MSB INVERTED
12:BSWD Byte swap data stored to SDRAM. 0:NORMAL 1:BYTE SWAP
11:Y8POS Location of Y signal when YCbCr 8bit data is input.0:EVEN PIXEL 1:ODD PIXEL
10:EXTRG External trigger.0:DIABLE 1:ENABLE
9:TRGSEL Signal that initializes SDRAM address when EXTRG = 1.
0: WEN bit (SYNCEN register).1:FID input port.
8:WENLOG Specifies CCD valid area.
0:Internal valid and WEN signals are ANDed logically.
1:Internal valid and WEN signals are ORed logically.
6:FIDMD Setting of FID detection function.
0:FID signal is latched at the VSYNC 1: FID signal is not latched.
5:BW656 The data width in REC656 input mode. 0:8BIT 1:10BIT
4:YCINSWP Y input (YIN[7:0]) and C input (CIN[7:0]) are swapped.
0:(NO_YCIN_SWAP) YIN[7:0] = Y signal / CIN[7:0] = C signal.
1:(YCIN_SWAP) YIN[7:0] = C signal / CIN[7:0] = Y signal.
15. Start Pixel Horizontal Register (FMTSPH) 针对CFA,即CMYG TO RGBG转换
16. Number Of Pixels Register (FMTLNH) 同上
17. Start Line Vertical Register (FMTSLV) 同上
18. Number of Lines Register (FMTLNV) 同上
19. Lens Shading Correction Configuration 1 Register (LSCCFG1) 同上
20. Lens Shading Correction Configuration 2 Register (LSCCFG2)
21. Lens Shading Correction - Center Position (H0) Register (LSCH0)
22. Lens Shading Correction - Center Position (V0) Register (LSCV0)
23. Lens Shading Correction - Horizontal Coefficients Register (LSCKH)
24. Lens Shading Correction - Vertical Coefficients Register (LSCKV)
25. Lens Shading Correction - Memory Control Register (LSCMEMCTL)
26. Lens Shading Correction - Memory Read Data Register (LSCMEMQ)
27. Defect Correction - Control Register (DFCCTL)
28. Defect Correction - Vertical Saturation Level Register (DFCVSAT)
29. Defect Correction - Memory Control Register (DFCMEMCTL)
30. Defect Correction - Set V Position Register (DFCMEM0)
31. Defect Correction - Set H Position Register (DFCMEM1)
32. Defect Correction - Set SUB1 Register (DFCMEM2)
33. Defect Correction - Set SUB2 Register (DFCMEM3)
34. Defect Correction - Set SUB3 Register (DFCMEM4)
35. Color Space Converter Enable Register (CSCCTL)
36. Color Space Converter - Coefficients #0 Register (CSCM0)-(CSCM7)
37. Data Offset Register (DATAOFST)
15-8 VOFST V direction data offset for defect correction and lens shading correction. Range: 0-255.
7-0 HOFST H direction data offset for defect correction and lens shading Correction. Range: 0-255.
二.IPIPEIF
1. IPIPE I/F Enable Register (ENABLE)
0:ENABLE SDRAM BUFFE读开始信号及产生SYNC信号 ,只有在INPSRC (CFG[3:2]) = 1, 2 or 3.下有用(CFG)
13-11:DATASFT SDRAM Read Data Shift (0_6) 当INPSRC = 1 or 2.有效
0 Output data (13:0) = read data(15:2)
1 Output data (13:0) = read data(14:1)
2 Output data (13:0) = read data(13:0)(
3 Output data (13:0) = read data(12:0) & "0"
4 Output data (13:0) = read data11:0) & "00"
5 Output data (13:0) = read data(10:0) & "000"
6 Output data (13:0) = read data(9:0) & "0000"
2. IPIPE I/F Configuration Register
10: CLKSEL
IPIPEIF & IPIPE Clock Select
This register is available when INPSRC = 1 or 3. Should code "0" when INPSRC = 0 or 2.
0 Pixel clock (PCLK)
1 Divided SDRAM clock as per CLKDIV
9: IALAW Inverse A-law Conversion
Applies inverse A-law (8bit to 10bit) conversion to the SDRAM data.
This register is available when= INPSRC 1 or 2.
0 Inverse alaw off
1 Inverse alaw on
8: PACK8IN 8-Bit Packed Mode INPSRC 1 or 2.有效
0 (NORMAL_16_BITS_PIXEL) 16 bits / pixel
1 (PACK_8_BITS_PIXEL) 8 bits / pixel
7 :AVGFILT Averaging Filter
It applies (1,2,1) filter for the RGB/YCbCr data.
0 Off
1 On
6-4: CLKDIV Clock Selection when Offline Mode (SDRAM Input? Mode)
IPIPEIF/IPIPE clock frequency = CLKDIV x VPSSCLK clock frequency(CLKSEL=1)
0-4:1/2-1/6 5:1/8 6:1/16 7:1/32
3-2: INPSRC CCD/YCbCr Data Port Selection
0 From CCD Controller
1 From SDRAM (raw data)
2 From CCD Controller & SDRAM (Darkframe)
3 From SDRAM (YCbCr data)
1: DECM Pixel Decimation
Decimation rate defined by RSZ register
0 No decimation
1 Decimate
0: ONESHOT One Shot Mode
This register is available when INPSRC = 1 or 3.
0 Continuous mode
1 One shot mode
3. IPIPE I/F Interval of HD / Start pixel in HD Register (PPLN)
4. IPIPE I/F Number of valid pixels per line Register (HNUM)
5. IPIPE I/F Number of Valid Lines per Frame Register (VNUM)
6. IPIPE I/F Memory Address (Upper) Register (ADDRU)
7. IPIPE I/F Memory Address (Lower) Register (ADDRL)
8. IPIPE I/F Address Offset of Each Line Register (ADOFS)
9. IPIPE I/F Horizontal Resizing Parameter Register (RSZ)(当水平像素大于1344时用到）
6-0 RSZ 10h-70h The Horizontal Resizing Parameter 水平RESIZE参数，16到112，以16/RSZ计算
10. IPIPE I/F Gain Parameter Register (GAIN)
三.IPIPE
1. IPIPE Enable Register (IPIPE_EN)
0:EN 在ONE-SHOT模式下,处理完一FRAME后EN自动清0
2. One Shot Mode Register (IPIPE_MODE)
1: WRT CAM_WEN mode selection.WRT=0则不管CAM_WEN,处理每一FRAME;WRT=1,则当CAM_WEN有效时处理(当时序有IPIPEIF产生时,应设为0)
0 ONESHOT One shot mode.
3. Input/Output Data Paths Register (IPIPE_DPATHS)
2 BYPASS Enable RAW-Bypass mode through IPIPE. 当设定时输入影像宽度可以达到4096PIXEL(只当FMT=1有效)
0-1 FMT Data Path through IPIPE.
0 (RAW2YUV) Bayer input, YCbCr (or RGB) output.
1 (RAW2RAW) Bayer input, Bayer output.
2 (RAW2BOX) Bayer input, Boxcar output.
3 (YUV2YUV) YCbCr (16bit) input, YCbCr (or RGB) output
4. Color Pattern Register (IPIPE_COLPAT)
5. Vertical Start Position Register (IPIPE_VST)
6. Vertical Processing Size Register (IPIPE_VSZ)
7. Horizontal Start Position Register (IPIPE_HST)
8. Horizontal Processing Size Register (IPIPE_HSZ)
9. ARM Gated Clock Control Register (GCL_ARM)
0 REG IPIPE MMR clock enable.
The on/off selection of the MMR interface clock which is used for ARM register accesses.
0 Off
1 On
10. CCD Gated Clock Control Register (GCL_CCD)
2 G2 IPIPE G2 clock enable.
The on/off selection of the clock which is used for the IPIPE processing of "CFA" to "422", "Histogram".
0 Off
1 On
1 G1 IPIPE G1 clock enable.
The on/off selection of the clock which is used for the IPIPE processing of "Defect Correction" to "WhiteBalance".
0 Off
1 On
0 G0 IPIPE G0 clock enable.
The on/off selection of the clock which is used for the IPIPE processing of "Boxcar".
0 Off
1 On
11. SDR Gated Clock Control Register (GCL_SDR)(RESIZER模块时钟能动，当为0时在RESIZER BYPASS模式）
0 RSZ IPIPE RSZ clock enable.
The on/off selection of the clock which is used for "Resize". The resizer operates in bypass mode when
this is off.
0 Off
1 On
12. Internal Table Selection Register (RAM_MODE)
13. Address Register (RAM_ADR)
14. Write Data Register (RAM_WDT)
15. Read Data Register (RAM_RDT)
16. Interrupt Enable Register (IRQ_EN)
17. Interval of IRQ-2 Register (IRQ_RZA)
12-0 VAL 0-1FFFh Interval of IRQ_2. Interrupt signal at every (VAL + 1) lines of Resize and RGB output.
18. Interval of IRQ-3 Register (IRQ_RZB)
12-0 VAL 0-1FFFh Interval of IRQ_3. Interrupt signal at every (VAL + 1) lines of Resize and RGB output
19. Defect Correction Enable Register (DFC_EN)
20. Copy Method Selection (from Top or from Bottom) Register (DFC_SEL)
21. Start Address in LUT Register (DFC_ADR)
22. Number of Available Entries in LUT Register (DFC_SIZ)
23. 2D Noise Filter Enable Register (D2F_EN)
24. Noise Filter Configuration Register (D2F_CFG)
25. Noise Filter LUT Values (Threshold) Register (D2F_THR[32])
26. Noise Filter LUT Values (Intensity) Register (D2F_STR[32])
27. PreFilter Enable Register (PRE_EN)
28. PreFilter Type Register (PRE_TYP)
29. Shift Value of Adaptive Gain Register (PRE_SHF)
30. Constant Gain or Adaptive Gain Slope Register (PRE_GAIN)
31. Threshold G Register (PRE_THR_G)
32. Threshold B Register (PRE_THR_B)
33. Threshold 1 Register (PRE_THR_1)
34. Digital Gain Register (WB2_DGN)
35. White Balance Gain Register (WB2_WG_R),(WB2_WG_GR),(WB2_WG_GB)(WB2 _WG_B)
36. Matrix Coefficient RR Register (RGB_MUL_RR),RGB_MUL_GR,RGB_MUL_BR),(RGB_MUL_RG)
37. Matrix Coefficient GG Register (RGB_MUL_GG),(RGB_MUL_BG),(RGB_MUL_RB),(RGB_MUL_GB),(RGB_MUL_BB)
38. R Output Offset Register (RGB_OFT_OR),(RGB_OFT_OG),(RGB_OFT_OB)
39. Gamma Correction Configuration Register (GMM_CFG)
40. Luminance Adjustment (Contrast and Brightness) Register (YCC_ADJ)
41. Matrix Coefficient RY Register (YCC_MUL_RY),(YCC_MUL_GY),(YCC_MUL_BY),(YCC_MUL_RCB),(YCC_MUL_GCB),(YCC_MUL_BCB),(YCC_MUL_RCR),(YCC_MUL_GCR),(YCC_MUL_BCR)
42. Y Output Offset Register (YCC_OFT_Y)
43. Cb Output Offset Register (YCC_OFT_CB)
44. Cr Output Offset Register (YCC_OFT_CR)
45. Saturation (Luminance Minimum) Register (YCC_Y_MIN)
46. Saturation (Luminance Maximum) Register (YCC_Y_MAX)
47. Saturation (Chrominance Minimum) Register (YCC_C_MIN)
48. Saturation (Chrominance Maximum) Register (YCC_C_MAX)
49. Chrominance Position (for 422 Down Sampler) Register (YCC_PHS)(当输入为YCBCR时）
50. Edge Enhancer Enable Register (YEE_EN)
51. MedianNR Enable Register (YEE_EMF)
52. HPF Shift Length Register (YEE_SHF)
53. HPF Coefficient 00 Register (YEE_MUL_00，01，02，10，11，12，20，21，22)
54. Fault Color Suppression Enable Register (FCS_EN)
55. Type selection of HPF Register (FCS_TYP)
56. Down Shift Size (HPF) Register (FCS_SHF_Y)
57. Down Shift Size (GAIN) Register (FCS_SHF_C)
58. Threshold Register (FCS_THR)
59. Intensity Register (FCS_SGN)
60. Processing Mode Register (RSZ_SEQ)
4 CRV Chroma sampling point change.
0 Chroma sampling point is not changed.
1 Chroma sampling point is changed from odd-numbered pixels to even-number pixels. The pixel the leftend is removed and the pixel at the right end is duplicated.
3 VRV Vertical reversal of output image.
0 Processed lines are output in the order of input (normal operation) in vertical direction.
1 The order of output data is flipped top to bottom.
2 HRV Horizontal reversal of output image.
0 Processed pixels are output in the order of input (normal operation) in horizontal direction.
1 The order of output data is flipped left to right.
1 TMM Terminal condition of vertical processing.
0 Output line number confined mode (normal mode). The module continues output of resized image untilthe number of output lines reaches the value set by RZA_O_VSZ and RZB_O_VSZ.
1 Input line number confined mode. The modules continues output of resized image until the inputnumber of input lines reads the value set by RZA_I_VSZ and RZB_I_VSZ. The numbers of output linesare output to RZA_V_SIZ_O and RZB_V_SIZ_O.
0 SEQ Operation mode of vertical processing.
0 Normal mode. The module clears register values and internal buffer values at VSYNC.
1 Continuous mode. Resizer holds values from the previous operation. This mode may only be used incombination with input line number confined mode (TMM=1).
61. Vertical Anti aliasing Filter Register (RSZ_AAL)
62. Resizer Enable Register (RSZ_EN)
63. One Shot Mode Register (RSZ_MODE)
0 OST One shot mode enable.
0 Continuous mode.
1 One shot mode.
64. Vertical Start Position of the Input Register (RSZ_I_VST)
11-0 VAL 0-FFFh Vertical start position of image processing.
After IPIPE_VST, the VAL line is processed as the first line in each image.(在IPIPE_VST之后计算)
65. Vertical Size of the Input Register (RSZ_I_VSZ)
11-0 VAL 0-FFFh Number of input lines. This value is used only in input line confined mode.(RSZ_SEQ[TMM] at 0108h).
The number of input lines is (VAL + 1).
66. Horizontal Start Position of the Input Register (RSZ_I_HST)
11-0 VAL 0-FFFh Horizontal start position of image processing.
(RSZ_I_HST[0] is held low so this value must be even). After IPIPE_HST, the VAL pixel is
processed as the first pixel.
67. Vertical Size of the Output Register (RSZ_O_VSZ)
11-0 VAL 0-FFFh Vertical size of the output image.
The number of output lines is (VAL + 1). (RSZ_O_VSZ[0] is held high so this value must be odd).
68. Horizontal Start Position of the Output Register (RSZ_O_HST)
11-0 VAL 0-FFFh Horizontal position of the first pixel to be output in processed image.
The first VAL pixels of the resized area in each line are discarded, and the next pixel becomes the first
to be output. (RSZ_O_HST[0] is held low so this value must be even).
69. Horizontal Size of the Output Register (RSZ_O_HSZ)
11-0 VAL 0-FFFh Horizontal size of output image. The number of pixel in each line is (VAL + 1).
RSZ[0]:Value must be lower than 1344 except in RAW passthu mode.
RSZ[1]:Value must be lower than 640. (RSZ_O_HSZ[0] is held high so this value must be odd).
70. Initial Phase of Vertical Resizing Process Register (RSZ_V_PHS)
13-0 VAL 0-3FFFh Initial value for the phase value in vertical resizing process. (Should be set to zero except in Frame
Division Mode-H). Valid range: 0-8191.
71. Phase of Last Value in Previous Resize Process Register (RSZ_V_PHS_O)
13-0 VAL 0-3FFFh Phase value of the last line in the previous resizing process. This value is only valid in input line
number confined mode ((RSZ_SEQ[TMM] at 0x0108).
72. Vertical Resize Parameter Register (RSZ_V_DIF)
13-0 VAL 0-3FFFh Vertical resize parameter. The actual resizing ratio is 256/VAL.
73. Actual Number of Output Lines Register (RSZ_V_SIZ_O)
12-0 VAL 0-1FFFh Number of actually produced lines in the previous resizing process
74. Initial Phase of Horizontal Resizing Process Register (RSZ_H_PHS)
一.CCDC
1.Synchronization Enable Register (SYNCEN)
0:VDHDEN
1:WEN
2.MODESET
15:FLDSTAT 0:ODD FIELD 1:EVEN FIELD
14:LPF 3-tap Low-Pass (anti-aliasing) filter for ccd data 0:off 1:on
13-12:INPMOD INPUT MODE 0:CCD RAW DATA 1:YCBCR 16BIT 2:YCBCR 8BIT
11:PACK8 0:NORMAL 16BIT TO SDRAM 1:PACK8 BIT TO SDRAM
10-8:DATASFT 0:NO SHIFT 1-6:SHIFT 1-6BIT
7:FLDMODE 0:NON-INTERFACED 1：INTERFACED （若EXWEN =1，则需为0）
6:DATAPOL 0:NORMAL 1:ONE'S CONPLEMENT
5:EXWEN 0:不用外部WEN 1:用外部VD/HD作为写SDRAM的信号
4:FLDPOL 0:POSITIVE 1:NEGATIVE
3:HDPOL 意思同上
2:VDPOL 意思同上
0:VDHDOUT 0:VD,HD INPUT 1:VD,HD OUTPUT
3. Horizontal Size Register (HSIZE)
12:ADR_UPDT SDRAM 地址更新方式0:自动增加 1:自动减少
11-0:LNOFST SDRAM中行尺寸,32BYTE为单位即16或32PIXELS
4.SDRAM Line Offset Register (SDOFST)
14：FIINV 0：NON INVERSE 1：INVERSE
13-12：FOFST Line offset value of odd field (FID = 1) 0-3：+1 - +4
11-9：LOFST0 Line offset values of even line and even field (FID = 0) 0-7：+1 - -4
8-6：LOFST1 Line offset values of odd line and even field (FID = 0) 同上
5-3：LOFST2 Line offset values of even line and odd field (FID = 1) 同上
2-0：LOFST3 Line offset values of odd line and odd field (FID = 1)同上
5.SDRAM Address - High Register (STADRH)
6.SDRAM Address - LOW Register (STADRL)
7.CCD Color Pattern Register (COLPTN)
8. CCD Gain Adjustment - R/Ye Register (RYEGAIN)
CCD Gain Adjustment - Gr/Cy Register (GRCYGAIN)
CCD Gain Adjustment - Gb/G Register (GBGGAIN)
CCD Gain Adjustment - B/Mg Register (BMGGAIN)
CCD Offset Adjustment Register (OFFSET)
9.Output Clipping Value Register (OUTCLIP)
10.VD Interrupt #0 Register (VDINT0) 中断设定行数
11. VD Interrupt #1 Register (VDINT1)
12. Gamma Correction Settings Register (GAMMAWD)
11-10:MFIL1 Median filter mode for IPIPE 0:no filer 1:average filer 2:median filer
9-8: MFIL1 Median Filter for SDRAM capture.值同上
5：CFAP CFA Pattern. 0：Mosaic 1：Stripe
4-2：GWDI Gamma Width Input (For A-LAW table & H3A port)
0：BITS 13-4 1：12-3 2：11-2 3：10-1 4：9-0
0：CCDTBL Apply Gamma (A-LAW) to CCDC data saved to SDRAM 0：DISABLE 1：ENABLE
13. REC656 Control Register (REC656IF)
1: ECCFVH FVH error correction enable 0:DISABLE 1:ENABLE
0: R656ON REC656 interface enable 0:DISABLE 1:ENABLE
14. CCD Configuration Register (CCDCFG)
15:VDLC Enable synchronizing function regs on VSYNC. 0:Latched on VSYNC. 1:NO LATCHED
13:MSBINVI MSB of Chroma input signal stored to SDRAM inverted.0:NORMAL 1:MSB INVERTED
12:BSWD Byte swap data stored to SDRAM. 0:NORMAL 1:BYTE SWAP
11:Y8POS Location of Y signal when YCbCr 8bit data is input.0:EVEN PIXEL 1:ODD PIXEL
10:EXTRG External trigger.0:DIABLE 1:ENABLE
9:TRGSEL Signal that initializes SDRAM address when EXTRG = 1.
0: WEN bit (SYNCEN register).1:FID input port.
8:WENLOG Specifies CCD valid area.
0:Internal valid and WEN signals are ANDed logically.
1:Internal valid and WEN signals are ORed logically.
6:FIDMD Setting of FID detection function.
0:FID signal is latched at the VSYNC 1: FID signal is not latched.
5:BW656 The data width in REC656 input mode. 0:8BIT 1:10BIT
4:YCINSWP Y input (YIN[7:0]) and C input (CIN[7:0]) are swapped.
0:(NO_YCIN_SWAP) YIN[7:0] = Y signal / CIN[7:0] = C signal.
1:(YCIN_SWAP) YIN[7:0] = C signal / CIN[7:0] = Y signal.
15. Start Pixel Horizontal Register (FMTSPH) 针对CFA,即CMYG TO RGBG转换
16. Number Of Pixels Register (FMTLNH) 同上
17. Start Line Vertical Register (FMTSLV) 同上
18. Number of Lines Register (FMTLNV) 同上
19. Lens Shading Correction Configuration 1 Register (LSCCFG1) 同上
20. Lens Shading Correction Configuration 2 Register (LSCCFG2)
21. Lens Shading Correction - Center Position (H0) Register (LSCH0)
22. Lens Shading Correction - Center Position (V0) Register (LSCV0)
23. Lens Shading Correction - Horizontal Coefficients Register (LSCKH)
24. Lens Shading Correction - Vertical Coefficients Register (LSCKV)
25. Lens Shading Correction - Memory Control Register (LSCMEMCTL)
26. Lens Shading Correction - Memory Read Data Register (LSCMEMQ)
27. Defect Correction - Control Register (DFCCTL)
28. Defect Correction - Vertical Saturation Level Register (DFCVSAT)
29. Defect Correction - Memory Control Register (DFCMEMCTL)
30. Defect Correction - Set V Position Register (DFCMEM0)
31. Defect Correction - Set H Position Register (DFCMEM1)
32. Defect Correction - Set SUB1 Register (DFCMEM2)
33. Defect Correction - Set SUB2 Register (DFCMEM3)
34. Defect Correction - Set SUB3 Register (DFCMEM4)
35. Color Space Converter Enable Register (CSCCTL)
36. Color Space Converter - Coefficients #0 Register (CSCM0)-(CSCM7)
37. Data Offset Register (DATAOFST)
15-8 VOFST V direction data offset for defect correction and lens shading correction. Range: 0-255.
7-0 HOFST H direction data offset for defect correction and lens shading Correction. Range: 0-255.
二.IPIPEIF
1. IPIPE I/F Enable Register (ENABLE)
0:ENABLE SDRAM BUFFE读开始信号及产生SYNC信号 ,只有在INPSRC (CFG[3:2]) = 1, 2 or 3.下有用(CFG)
13-11:DATASFT SDRAM Read Data Shift (0_6) 当INPSRC = 1 or 2.有效
0 Output data (13:0) = read data(15:2)
1 Output data (13:0) = read data(14:1)
2 Output data (13:0) = read data(13:0)(
3 Output data (13:0) = read data(12:0) & "0"
4 Output data (13:0) = read data11:0) & "00"
5 Output data (13:0) = read data(10:0) & "000"
6 Output data (13:0) = read data(9:0) & "0000"
2. IPIPE I/F Configuration Register
10: CLKSEL
IPIPEIF & IPIPE Clock Select
This register is available when INPSRC = 1 or 3. Should code "0" when INPSRC = 0 or 2.
0 Pixel clock (PCLK)
1 Divided SDRAM clock as per CLKDIV
9: IALAW Inverse A-law Conversion
Applies inverse A-law (8bit to 10bit) conversion to the SDRAM data.
This register is available when= INPSRC 1 or 2.
0 Inverse alaw off
1 Inverse alaw on
8: PACK8IN 8-Bit Packed Mode INPSRC 1 or 2.有效
0 (NORMAL_16_BITS_PIXEL) 16 bits / pixel
1 (PACK_8_BITS_PIXEL) 8 bits / pixel
7 :AVGFILT Averaging Filter
It applies (1,2,1) filter for the RGB/YCbCr data.
0 Off
1 On
6-4: CLKDIV Clock Selection when Offline Mode (SDRAM Input? Mode)
IPIPEIF/IPIPE clock frequency = CLKDIV x VPSSCLK clock frequency(CLKSEL=1)
0-4:1/2-1/6 5:1/8 6:1/16 7:1/32
3-2: INPSRC CCD/YCbCr Data Port Selection
0 From CCD Controller
1 From SDRAM (raw data)
2 From CCD Controller & SDRAM (Darkframe)
3 From SDRAM (YCbCr data)
1: DECM Pixel Decimation
Decimation rate defined by RSZ register
0 No decimation
1 Decimate
0: ONESHOT One Shot Mode
This register is available when INPSRC = 1 or 3.
0 Continuous mode
1 One shot mode
3. IPIPE I/F Interval of HD / Start pixel in HD Register (PPLN)
4. IPIPE I/F Number of valid pixels per line Register (HNUM)
5. IPIPE I/F Number of Valid Lines per Frame Register (VNUM)
6. IPIPE I/F Memory Address (Upper) Register (ADDRU)
7. IPIPE I/F Memory Address (Lower) Register (ADDRL)
8. IPIPE I/F Address Offset of Each Line Register (ADOFS)
9. IPIPE I/F Horizontal Resizing Parameter Register (RSZ)(当水平像素大于1344时用到）
6-0 RSZ 10h-70h The Horizontal Resizing Parameter 水平RESIZE参数，16到112，以16/RSZ计算
10. IPIPE I/F Gain Parameter Register (GAIN)
三.IPIPE
1. IPIPE Enable Register (IPIPE_EN)
0:EN 在ONE-SHOT模式下,处理完一FRAME后EN自动清0
2. One Shot Mode Register (IPIPE_MODE)
1: WRT CAM_WEN mode selection.WRT=0则不管CAM_WEN,处理每一FRAME;WRT=1,则当CAM_WEN有效时处理(当时序有IPIPEIF产生时,应设为0)
0 ONESHOT One shot mode.
3. Input/Output Data Paths Register (IPIPE_DPATHS)
2 BYPASS Enable RAW-Bypass mode through IPIPE. 当设定时输入影像宽度可以达到4096PIXEL(只当FMT=1有效)
0-1 FMT Data Path through IPIPE.
0 (RAW2YUV) Bayer input, YCbCr (or RGB) output.
1 (RAW2RAW) Bayer input, Bayer output.
2 (RAW2BOX) Bayer input, Boxcar output.
3 (YUV2YUV) YCbCr (16bit) input, YCbCr (or RGB) output
4. Color Pattern Register (IPIPE_COLPAT)
5. Vertical Start Position Register (IPIPE_VST)
6. Vertical Processing Size Register (IPIPE_VSZ)
7. Horizontal Start Position Register (IPIPE_HST)
8. Horizontal Processing Size Register (IPIPE_HSZ)
9. ARM Gated Clock Control Register (GCL_ARM)
0 REG IPIPE MMR clock enable.
The on/off selection of the MMR interface clock which is used for ARM register accesses.
0 Off
1 On
10. CCD Gated Clock Control Register (GCL_CCD)
2 G2 IPIPE G2 clock enable.
The on/off selection of the clock which is used for the IPIPE processing of "CFA" to "422", "Histogram".
0 Off
1 On
1 G1 IPIPE G1 clock enable.
The on/off selection of the clock which is used for the IPIPE processing of "Defect Correction" to "WhiteBalance".
0 Off
1 On
0 G0 IPIPE G0 clock enable.
The on/off selection of the clock which is used for the IPIPE processing of "Boxcar".
0 Off
1 On
11. SDR Gated Clock Control Register (GCL_SDR)(RESIZER模块时钟能动，当为0时在RESIZER BYPASS模式）
0 RSZ IPIPE RSZ clock enable.
The on/off selection of the clock which is used for "Resize". The resizer operates in bypass mode when
this is off.
0 Off
1 On
12. Internal Table Selection Register (RAM_MODE)
13. Address Register (RAM_ADR)
14. Write Data Register (RAM_WDT)
15. Read Data Register (RAM_RDT)
16. Interrupt Enable Register (IRQ_EN)
17. Interval of IRQ-2 Register (IRQ_RZA)
12-0 VAL 0-1FFFh Interval of IRQ_2. Interrupt signal at every (VAL + 1) lines of Resize and RGB output.
18. Interval of IRQ-3 Register (IRQ_RZB)
12-0 VAL 0-1FFFh Interval of IRQ_3. Interrupt signal at every (VAL + 1) lines of Resize and RGB output
19. Defect Correction Enable Register (DFC_EN)
20. Copy Method Selection (from Top or from Bottom) Register (DFC_SEL)
21. Start Address in LUT Register (DFC_ADR)
22. Number of Available Entries in LUT Register (DFC_SIZ)
23. 2D Noise Filter Enable Register (D2F_EN)
24. Noise Filter Configuration Register (D2F_CFG)
25. Noise Filter LUT Values (Threshold) Register (D2F_THR[32])
26. Noise Filter LUT Values (Intensity) Register (D2F_STR[32])
27. PreFilter Enable Register (PRE_EN)
28. PreFilter Type Register (PRE_TYP)
29. Shift Value of Adaptive Gain Register (PRE_SHF)
30. Constant Gain or Adaptive Gain Slope Register (PRE_GAIN)
31. Threshold G Register (PRE_THR_G)
32. Threshold B Register (PRE_THR_B)
33. Threshold 1 Register (PRE_THR_1)
34. Digital Gain Register (WB2_DGN)
35. White Balance Gain Register (WB2_WG_R),(WB2_WG_GR),(WB2_WG_GB)(WB2 _WG_B)
36. Matrix Coefficient RR Register (RGB_MUL_RR),RGB_MUL_GR,RGB_MUL_BR),(RGB_MUL_RG)
37. Matrix Coefficient GG Register (RGB_MUL_GG),(RGB_MUL_BG),(RGB_MUL_RB),(RGB_MUL_GB),(RGB_MUL_BB)
38. R Output Offset Register (RGB_OFT_OR),(RGB_OFT_OG),(RGB_OFT_OB)
39. Gamma Correction Configuration Register (GMM_CFG)
40. Luminance Adjustment (Contrast and Brightness) Register (YCC_ADJ)
41. Matrix Coefficient RY Register (YCC_MUL_RY),(YCC_MUL_GY),(YCC_MUL_BY),(YCC_MUL_RCB),(YCC_MUL_GCB),(YCC_MUL_BCB),(YCC_MUL_RCR),(YCC_MUL_GCR),(YCC_MUL_BCR)
42. Y Output Offset Register (YCC_OFT_Y)
43. Cb Output Offset Register (YCC_OFT_CB)
44. Cr Output Offset Register (YCC_OFT_CR)
45. Saturation (Luminance Minimum) Register (YCC_Y_MIN)
46. Saturation (Luminance Maximum) Register (YCC_Y_MAX)
47. Saturation (Chrominance Minimum) Register (YCC_C_MIN)
48. Saturation (Chrominance Maximum) Register (YCC_C_MAX)
49. Chrominance Position (for 422 Down Sampler) Register (YCC_PHS)(当输入为YCBCR时）
50. Edge Enhancer Enable Register (YEE_EN)
51. MedianNR Enable Register (YEE_EMF)
52. HPF Shift Length Register (YEE_SHF)
53. HPF Coefficient 00 Register (YEE_MUL_00，01，02，10，11，12，20，21，22)
54. Fault Color Suppression Enable Register (FCS_EN)
55. Type selection of HPF Register (FCS_TYP)
56. Down Shift Size (HPF) Register (FCS_SHF_Y)
57. Down Shift Size (GAIN) Register (FCS_SHF_C)
58. Threshold Register (FCS_THR)
59. Intensity Register (FCS_SGN)
60. Processing Mode Register (RSZ_SEQ)
4 CRV Chroma sampling point change.
0 Chroma sampling point is not changed.
1 Chroma sampling point is changed from odd-numbered pixels to even-number pixels. The pixel the leftend is removed and the pixel at the right end is duplicated.
3 VRV Vertical reversal of output image.
0 Processed lines are output in the order of input (normal operation) in vertical direction.
1 The order of output data is flipped top to bottom.
2 HRV Horizontal reversal of output image.
0 Processed pixels are output in the order of input (normal operation) in horizontal direction.
1 The order of output data is flipped left to right.
1 TMM Terminal condition of vertical processing.
0 Output line number confined mode (normal mode). The module continues output of resized image untilthe number of output lines reaches the value set by RZA_O_VSZ and RZB_O_VSZ.
1 Input line number confined mode. The modules continues output of resized image until the inputnumber of input lines reads the value set by RZA_I_VSZ and RZB_I_VSZ. The numbers of output linesare output to RZA_V_SIZ_O and RZB_V_SIZ_O.
0 SEQ Operation mode of vertical processing.
0 Normal mode. The module clears register values and internal buffer values at VSYNC.
1 Continuous mode. Resizer holds values from the previous operation. This mode may only be used incombination with input line number confined mode (TMM=1).
61. Vertical Anti aliasing Filter Register (RSZ_AAL)
62. Resizer Enable Register (RSZ_EN)
63. One Shot Mode Register (RSZ_MODE)
0 OST One shot mode enable.
0 Continuous mode.
1 One shot mode.
64. Vertical Start Position of the Input Register (RSZ_I_VST)
11-0 VAL 0-FFFh Vertical start position of image processing.
After IPIPE_VST, the VAL line is processed as the first line in each image.(在IPIPE_VST之后计算)
65. Vertical Size of the Input Register (RSZ_I_VSZ)
11-0 VAL 0-FFFh Number of input lines. This value is used only in input line confined mode.(RSZ_SEQ[TMM] at 0108h).
The number of input lines is (VAL + 1).
66. Horizontal Start Position of the Input Register (RSZ_I_HST)
11-0 VAL 0-FFFh Horizontal start position of image processing.
(RSZ_I_HST[0] is held low so this value must be even). After IPIPE_HST, the VAL pixel is
processed as the first pixel.
67. Vertical Size of the Output Register (RSZ_O_VSZ)
11-0 VAL 0-FFFh Vertical size of the output image.
The number of output lines is (VAL + 1). (RSZ_O_VSZ[0] is held high so this value must be odd).
68. Horizontal Start Position of the Output Register (RSZ_O_HST)
11-0 VAL 0-FFFh Horizontal position of the first pixel to be output in processed image.
The first VAL pixels of the resized area in each line are discarded, and the next pixel becomes the first
to be output. (RSZ_O_HST[0] is held low so this value must be even).
69. Horizontal Size of the Output Register (RSZ_O_HSZ)
11-0 VAL 0-FFFh Horizontal size of output image. The number of pixel in each line is (VAL + 1).
RSZ[0]:Value must be lower than 1344 except in RAW passthu mode.
RSZ[1]:Value must be lower than 640. (RSZ_O_HSZ[0] is held high so this value must be odd).
70. Initial Phase of Vertical Resizing Process Register (RSZ_V_PHS)
13-0 VAL 0-3FFFh Initial value for the phase value in vertical resizing process. (Should be set to zero except in Frame
Division Mode-H). Valid range: 0-8191.
71. Phase of Last Value in Previous Resize Process Register (RSZ_V_PHS_O)
13-0 VAL 0-3FFFh Phase value of the last line in the previous resizing process. This value is only valid in input line
number confined mode ((RSZ_SEQ[TMM] at 0x0108).
72. Vertical Resize Parameter Register (RSZ_V_DIF)
13-0 VAL 0-3FFFh Vertical resize parameter. The actual resizing ratio is 256/VAL.
73. Actual Number of Output Lines Register (RSZ_V_SIZ_O)
12-0 VAL 0-1FFFh Number of actually produced lines in the previous resizing process
74. Initial Phase of Horizontal Resizing Process Register (RSZ_H_PHS)
VPFE寄存器说明
VPFE
1.OVERVIEW
1.1 CCDC
1）产生SD，HD时序信号
2）可编程镜头阴影校正（ Lens Shading Correction）.
3）支持BT656，YCBCR422（8BIT，16BIT，WITH HS，VS），及14BIT RAW DATA FROM CCD/CMOS
4) 可编程14BIT 到8BIT输出
5）可通过外部写能动信号EN控制向DDR写数据
6）SENSOR CLK可达75MHZ，若用到H3A，则只能达67.5MHZ
7）DEFECT CORRECT
1.2.H3A
1）auto white balance and auto eexposure by collecting metrics（统计）
2）读写DDR
3）只接收RAW DATA
1.3.IPIPE
1）只接收RAW DATA ，且转换14BIT RAW DATA为YCBCR422或YCRCR422 RESIZE
2）支持RGB Bayer pattern，经过彩色空间转换也支持CMYG
3）每个分量增益控制
4）可编程的RGB TO YCBCR的转换系数
5）可配置成仅RESIZE模式，即直接YCBCR422 RESIZE，不经过其它模块处理
6）RGB (32bit/16bit) output to SDRAM
7）要求至少BLANK 8PIXEL/行，4行 BLANK，在ONE SHOT 下，至少10行 BLANK，在处理之后
8）最大支持1344PIXEL 输入输出宽度
9）DEFECT CORRECT
1.4.IPIPEIF
1）读CCDC，SDRAM，写IPIPE
2）重新调整 HD, VD, and PCLK timing to the IPIPE input.
3）dark-frame subtract黑色帧消除法降噪（用于长时间瀑光引起的噪声点）
2.引脚IO 接口
1. YIN[7..0]/CCDIN[7..0]
2. CIN[5..0]/CCDIN[13..0]
3.PCLK
4.CAM_HD,CAM_VD
5.CAM_WEN_FIELD:/设 CCD Write Enable/Field ID signal
1）作FIELD标识信号，FLDMODE定类型提供，由CCD/CMOSFIDMD/FLDPOL
2）作WEN用，EXWEN打开，WENLOG设定AND 或 OR，与在SPH, NPH, SLV, NLV内的有效像素相AND或OR
RAM模式引脚:
以上全需用到
另少于14BIT时,一般用CCD[13..0]高位,舍去底位,当用时SPI时除外
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引脚配置REG: PINMUX0(VPFE.PDF PAGE38)
3。VPFE/ISP Integration
VPSS Events:9个作为中断送ARM，4个作为EVENT送EDMA
Number Acronym Module Description
0 CCDC VDINT0 CCDC Triggered after a programmable number of input lines for each frame.
1 CCDC VDINT1 CCDC Triggered after a programmable number of input lines for each frame.
2 CCDC VDINT2 CCDC Triggered at the rising edge of WEN signal
3 H3AINT H3A Triggered at the end of AF or AEW writes to DDR for each frame
4 VENCINT VENC Triggered at the rising edge of VSYNC
5 OSDINT OSD Triggered at the end of each frame read from DDR
6 IPIPEIFINT IPIPEIF Triggered at the rising edge of VD if enabled
7 IPIPE_INT0_HST IPIPE Triggered when Histogram processing is finished for each frame
8 IPIPE_INT1_SDR IPIPE Triggered when writes to DDR are finished for each frame
9 IPIPE_INT2_RZA IPIPE Triggered when the number of lines programmed has been output of RZA
10 IPIPE_INT3_RZB IPIPE Triggered when the number of lines programmed has been output of RZB
12 IPIPE_INT5_MMR IPIPE Triggered when MMR modifications for the next frame can be made
中断：VPSSBL.INTSEL选择
INT Number Acronym
0 VPSSINT0
1 VPSSINT1
2 VPSSINT2
3 VPSSINT3
4 VPSSINT4
5 VPSSINT5
6 VPSSINT6
7 VPSSINT7
8 VPSSINT8
事件：VPSSBL.EVTSEL选择
Event Number Binary Event Name
4 0000100 VPSSEVT1
5 0000101 VPSSEVT2
6 0000110 VPSSEVT3
7 0000111 VPSSEVT4
VPSS REG：
VPFE Module Register Map
VPSS Registers Address Range Size
VPSSCLK 0x01C70000 0x01C7007F 128B
H3A 0x01C70080 0x01C700FF 128B
IPIPEIF 0x01C70100 0x01C701FF 256B
OSD 0x01C70200 0x01C702FF 256B
VENC 0x01C70400 0x01C705FF 512B
CCDC 0x01C70600 0x01C707FF 512B
VPSSBL 0x01C70800 0x01C708FF 256B
IPIPE 0x01C71000 0x01C73FFF 12K-
-------------------------------------------------------------------------
4 。VPFE/ISP Functional Description
4.1 CCDC
参数：MODESET.INPMOD输出到DDR的数据选择，YCBCR或RGB
RAW模式时序参数：HDW，VDW，PPLN，HLPFR （从AFE来）
RAW模式时CCDCFG.YCINSWP=0
4.1.2.1 DIGITAL CLAMP
CLAMP的黑电平可用常量也可从像素中计算得到,也可从CCD SENSOR的上黑边，左黑边提取基量
以求平均值计算。
参数：CLAMP.OBST 黑像素开始点；CLAMP.OBSLEN每行的用来求平均的像素数；DCSUB.OBSLN求平均的行数
4.1.2.2 Color Space Conversion
CSCCTL[0]开启。由乘加器，LINE MEMORY组成，CMYG--》RGBG
FMTSPH, FMTLNH, FMTSLV, and FMTLNV指定数据区域
转换后数据会有一行LATENCY（延迟）。
最后一行至少要有一无效像素，一FRAME中至少要有一无效行
4.1.2.3 Defect Correction：坏点校正
DFCCTL[0]开启，可校正1024个点
4.1.2.4 Lens Shading Correction：镜头阴影校正
LSCCFG[0]开启，由于镜头中心较亮，向边缘渐暗。由此而校正
4.1.2.5 Black Level Compensation：太亮，太暗补偿
BLKCMP0.R_YE, BLKCMP0.GR_CY, BLKCMP1.GB_G, BLKCMP1.B_MG)
4.1.2.6 Median Filter：中央滤波。一路送SDRAM，另一路送IPIPE，可单独能动
1. Average Filter Configuration
2. Median Filter Configuration
GAMMAWD.MFILT1 and GAMMAWD.MFILT2
4.1.2.7 SDRAM RAW Output Formatting
4.1.4 Data Output Control
• SDOFST.FIINV – invert interpretation of the Field ID signal
• SDOFST.FIINV – invert interpretation of the Field ID signal
• SDOFST.LOFTS0 – offset, in lines, between even lines on even fields (field 0)
• SDOFST.LOFTS1 – offset, in lines, between odd lines on even fields (field 0)
• SDOFST.LOFTS2 – offset, in lines, between even lines on odd fields (field 1)
• SDOFST.LOFTS3 – offset, in lines, between odd lines on odd fields (field 1)
4.2 IPIPEIF
参数：HDW=8PIXEL，VDW=4LINE（CONTINUE）OR 10LINE（ONE SHOT），PPLN=HD 间隔，LPFR=VD 间隔>1 LINE，HNUM=水平有效像素（从HD上升沿开始？？？），VNUM=垂直有效像素（从VD下降沿开始，即隔4或10LINE）
4.2.1.1 CCDC RAW Input Mode (CFG.INPSRC = 0)
14BIT
4.2.1.2 SDRAM RAW Input Mode (CFG.INPSRC = 1h)
从SDRAM中读取8BIT或16BIT，8BIT为经过A-LAW压缩的，可设CFG.IALAW解压，也可填0补齐
4.2.1.3 CCDC RAW Input With Dark Frame Subtract From SDRAM Mode (CFG.INPSRC = 2h)
IPIPEIF INPUT = CCDC RAW INPUT - SDRAM INPUT
此时PPLN，LPFR的意义与其它输入模式不同，表示从CCDC DATA中减去时的水平，垂直方向的起始位置
4.2.1.4 SDRAM YCbCr 4:2:2 Input Mode (CFG.INPSRC = 3h)
16BIT YCbCr 4:2:2 data
4.2.2 时序产生
当输入为0或2时，HD/VD/WEN ，PCLK由CCDC提供， 为1或3时，IPIEIF产生HD/VD（基于LPFR and PPLN），PCLK可继续用CCDC的PCLK（CFG.CLKSEL=0），也可自已产生（CFG.CLKSEL=1）（用VPSSCLK分频CFG.CLKDIV），产生PCLK时要考虑下面IPIPE RESIZE时最大时钟要求及SDRAM实时操作要求
当CFG.INPSRC非0时，IPIPE I/F SDRAM data读及时序产生即可在ONE-SHOT 下，也可在CONTINUE模式下（(ENABLE.ENABLE）
当输入大于1344PIXEL时开启CFG.DECM设定比例系数以缩小到1344以下
4.3 IPIPE
参数：IPIPE_HST,IPIPE_VST定义开始点（与HD，VD上升沿为原点），IPIPE_HSZ, IPIPE_VSZ定义要处理的数据区域大小
IPIPE_COLPAT定义处理数据的Color pattern
Input Modes (IPIPE_DPATHS.FMT)
0: RAW to YCbCr
1: RAW to RAW
2: RAW to Boxcar
3: YCbCr to YCbCr
In RAW pass through mode,可以支持最大4096PIXEL/LINE，直接写到SDRAM
4.3.3 Defect Correction
4.3.4 Noise Filter
4.3.5 Pre Filter
为了减少LINE-CRAWLING，只针对green pixels.有两种方式（PRE_TYP选择）：1.常量 2.算法
4.3.6 White Balance
白平衡就是调整增益，有两种：
1.Digital gain调整影像总亮度，x 0 – x 3.996 (step = 1/256)
2. white balance gains 调整CFA中每个分量的增益，x 0 – x 7.992 (step = 1/128)
4.3.7 CFA Interpolation
由 Bayer RGB转换成RGB 4:4:4 data
4.3.8 RGB2RGB Blending（混合）
RGB混合，即增加一OFFSET，调成人类的色彩光谱。(RGB_MUL_[R,G,B][R,G,B], & RGB_OFT_[R,G,B])
4.3.9 Gamma Correction Module
摄像时亮度与电压成非线性关系，称此为GAMMA曲线，GAMMA校正即是校正此非线性
有三个通路：1.BYPASS 2. 从RAM TABLE 3. 从ROM TABLE
4.3.10 RGB2YCbCr Conversion Module
YCC_MUL_[R,G,B][Y,CB,CR], and YCC_OFT_[Y,CB,CR]
4.3.11 4:2:2 Conversion Module
转换成YCBCR422格式
4.3.12 2-D Edge Enhancer
针对亮度信号，提高IMAGE质量。YEE_EN.EN开启。用一高通FILER来获取图像边缘，FILER系数可编程(YEE_MUL_[0,1,2][0,1,2])，输出可下SHIFT（YEE_SHF.SHF）。增加RAM表值可加强sharpness
4.3.13 Median NR
用来减少边缘强度的pseudo peak（假峰值），YEE_EMF.EN开启
4.3.14 Chrominance Suppression
FCS_EN.EN开启。在图像的亮度很强区域，可能会有一两个色彩通道饱和，但其它色彩没有，这样就会造成假色彩，如最常出现的就是原本是白色的却出现的是粉红色， 色度抑制可减少假色彩。
4.3.15 Horizontal and Vertical Resize Module
范围： x1/16 scale-down to x8
参数：RSZ[n].RSZ_H_TYP类型选择，HRSZ (RSZ[n].RSZ_H_DIF) and VRSZ (RSZ[n].RSZ_V_DIF)比例，上下限为32-4096，对应X8-X1/16，实际以256/HRSZ，256/VRSZ计算，影像输出尺寸最大为1344 pixels/line for RSZ[0] and 640 pixels/line for RSZ[1].
Vertical resize有两种模式：输入行号模式（RSZ_SEQ.TMM = 1)，连续模式。RSZ[n].RSZ_V_PHS_O定义最后输出位置
4.3.16 Output Interface
YCC_Y_MAX, YCC_Y_MIN, YCC_C_MAX, and YCC_C_MIN 定义Y，C大小范围，YCBCR422 TO YCBCR444，TO RGB，输出32BIT
4.3.17 RGB Converter
在H/V RESIZER中，YCBCR422通过线性插值，转成YCBCR444，由于此关系，第一行的一前一后两个像素会丢失，即RESIZE后会比想要的少两个像素。
在SDRAM BURST（256BIT）时以数据打包方式访问，有两种打包方式，32BIT，16BIT，(RSZ[n].RGB_TYP.TYP选择。32BIT时输出RGB各8位，及8BIT alpha value(在RSZ[n].RGB_BLD设定）；In 16-bit mode, R (5-bit), G (6-bit), and B (5-bit)输入到SDRAM。
4.4 H3A
5 Programming Model
VPFE Memory Master Selection
Shared Memory Register Field Settings
Shared Read Buffer (SRB) PCR.RBLCTRL 0: IPIPEIF
1: Reserved
2: H3A
Shared Write Buffer (SWB) PCR.WBLCTRL 0: IPIPEIF
1: Reserved
DFC Table MEMCTRL.DFCCTRL 0: IPIPE
1: CCDC
RSZ Line Memory MEMCTRL.RSZ_CTRL 0: IPIPEIF
1: Reserved
5.4 编程CCDC
模块能动：SYNCEN.VDHDEN能动CCDC，在能动之前需先设置一些REG。
SYNCEN.WEN 写SDRAM能动
若CCDC为MASTER MODE，则当SYNCEN.VDHDEN 后立即进行数据处理
若CCDC为SLAVE MODE, 则 SYNCEN.VDHDEN 应先于外部设备打开,以免数据丢失
设置顺序:
1. Set Data output address (STADRH & STADRL).
2. Enable HD/VD and WEN at the same time (MODESET.WEN & SYNCEN.VDHDEN)
中断:
VDINT0, VDINT1, and VDINT2
VDINT0,VDINT1达到VDINT.VDINT0 and VDINT.VDINT1中的行数后中断
VDINT2 以 CAM_WEN_FIELD为参考,在下降沿中断
MODESET.FLDSTAT场状态指示
REG整体上可分两种：
Shadowed Registers (event latched registers)—可随时读写，但只有当一定的事件发生时才起作用
Busy-Writeable Registers—可随时读写，即时发生作用
5.5 Programming the Image Pipe Interface (IPIPEIF)
模块能动：ENABLE.ENABLE ，当输入为CCDC RAW时，不需能动，CCDC 送什么就处理什么
当输入为SDRAM时CFG.ONESHOT定义ONESHOT模式还是CONTINOUS模式。在ONESHOT模式，只有一FRAME被处理，且ENABLE.ENABLE自动清0
会产生一 IPIPEIF event to the VPSSBL
5.6 Programming the Image Pipe (IPIPE)
模块能动：IPIPE_EN.EN
IPIPE EVENT
IRQ0 Final pixel from each frame is flushed from the image pipe (not resizer) and histogram completion event
IRQ1 SDRAM Write Completion Event
IRQ2 RZA Interval Completion Event
IRQ3 RZB Interval Completion Event
IRQ5 Register Update Ready Notification Event
5.6.1.2.1 Resizer Bypass Mode
Since the YCbCr data still passes through the RZA block in resizer bypass mode, the following registers
must be set accordingly:
GCK_SDR = 0 RSZ[0].RSZ_V_DIF = 256
RSZ_SEQ.SEQ = 0 RSZ[0].RSZ_H_PHS = 0
RSZ_SEQ.TMM = 0 RSZ[0].RSZ_H_DIF = 256
RSZ_AAL = 0 RSZ[0].RSZ_H_LSE = 0
RSZ[0].RSZ_O_HPS = 0 RSZ[1].RSZ_EN = 0
RSZ[0].RSZ_V_PHS = 0
5.6.1.2.2 RAW input, RAW output Mode (IPIPE_DPATHS.FMT = 1)
In this mode, the RAW data bypasses the RAW to YCbCr processes (see Figure 37), but since it still
passes through the YCbCr processing blocks, the following registers must be set accordingly:
IPIPE_DPATHS.FMT = 1 YEE_EN = 0 RSZ[0].RSZ_V_DIF = 256
BOX_EN = 0 FCS_EN = 0 RSZ[0].RSZ_H_PHS = 0
YCC_ADJ.CTR = 16 RSZ_SEQ.TMM = 0 RSZ[0].RSZ_H_DIF = 256
YCC_ADJ.BRT = 0 RSZ[0].RSZ_EN = 1 RSZ[0].RSZ_H_TYP = 0
YCC_Y_MIN = 0 RSZ[0].RSZ_I_VPS = 0 RSZ[0].RSZ_H_LSE = 0
YCC_Y_MAX = 255 RSZ[0].RSZ_I_HPS = 0 RSZ[0].RSZ_H_LPF = 0
YCC_C_MIN = 0 RSZ[0].RSZ_O_HPS = 0 RSZ[0].RSZ_RGB_EN = 0
YCC_C_MAX = 255 RSZ[0].RSZ_V_PHS = 0 RSZ[1].RSZ_EN = 0
5.6.1.3.1 Read/Write Procedures
The IPIPE internal memory values can be written, read, and written after read. If multiple values need to
be set in incremental addresses, then the RAM_MODE.ADR bit can be set so that only the first address
needs to be set and subsequent reads/writes will auto-increment the internal address. The following
procedures should be followed to access the internal memories:
For memory write:
1. Write to RAM_MODE: set memory selection and set EXT = 0 andWDT = 1.
2. Write to RAM_ADR: set starting offset into memory.
3. Write to RAM_WDT: Write data.
For memory read:
1. Write to RAM_MODE: set memory selection and set EXT = 0 andWDT = 0.
2. Write to RAM_ADR: set starting offset into memory.
3. Write to RAM_WDT: Write dummy data.
4. Read the data of the internal memory from RAM_RDT.
For memory write after read:
1. Write to RAM_MODE: set memory selection and set EXT = 0 andWDT = 1.
2. Write to RAM_ADR: set starting offset into memory.
3. Write to RAM_WDT: Write data.
4. Read the data of the internal memory from RAM_RDT.
5.7 Programming the Hardware 3A (H3A)
模块能动： PCR.AF_EN ，PCR.AEW_EN
当输入为SDRAM时，ONE-SHOT模式处理.若要处理每FRAME,则需设定PCR.SDR_FETCH_EN
当输入为CCDC时, CONTINUOUS模式处理,此时依据CCDC的时序来处理.应先CCDC能动
此模块处理完一FRAME后,可产生一中断和一EVENT
5.8 Programming the Buffer Logic (VPSSBL and VPSSCLK Registers)
VPSSBL and VPSSCLK Required Configuration Parameters
Function Configuration Required
CCDC VPSSBL.MEMCTRL.DFCCTRL
VPSSCLK.CLKCTRL.CCDCCLK
IPIPEIF VPSSBL.PCR.RBLCTRL
VPSSCLK.CLKCTRL.IPIPECLK
IPIPE VPSSBL.PCR.WBLCTRL
VPSSBL.MEMCTRL.IPIPE_WD_EN
VPSSBL.MEMCTRL.RESZ_CTRL
VPSSBL.MEMCTRL.DFCCTRL
VPSSCLK.CLKCTRL.IPIPECLK
H3A VPSSBL.PCR.RBLCTRL
VPSSCLK.CLKCTRL.H3ACLK
中断及事件选择VPSSBL.INTSEL and VPSSBL.EVTSEL
1.OVERVIEW
1.1 CCDC
1）产生SD，HD时序信号
2）可编程镜头阴影校正（ Lens Shading Correction）.
3）支持BT656，YCBCR422（8BIT，16BIT，WITH HS，VS），及14BIT RAW DATA FROM CCD/CMOS
4) 可编程14BIT 到8BIT输出
5）可通过外部写能动信号EN控制向DDR写数据
6）SENSOR CLK可达75MHZ，若用到H3A，则只能达67.5MHZ
7）DEFECT CORRECT
1.2.H3A
1）auto white balance and auto eexposure by collecting metrics（统计）
2）读写DDR
3）只接收RAW DATA
1.3.IPIPE
1）只接收RAW DATA ，且转换14BIT RAW DATA为YCBCR422或YCRCR422 RESIZE
2）支持RGB Bayer pattern，经过彩色空间转换也支持CMYG
3）每个分量增益控制
4）可编程的RGB TO YCBCR的转换系数
5）可配置成仅RESIZE模式，即直接YCBCR422 RESIZE，不经过其它模块处理
6）RGB (32bit/16bit) output to SDRAM
7）要求至少BLANK 8PIXEL/行，4行 BLANK，在ONE SHOT 下，至少10行 BLANK，在处理之后
8）最大支持1344PIXEL 输入输出宽度
9）DEFECT CORRECT
1.4.IPIPEIF
1）读CCDC，SDRAM，写IPIPE
2）重新调整 HD, VD, and PCLK timing to the IPIPE input.
3）dark-frame subtract黑色帧消除法降噪（用于长时间瀑光引起的噪声点）
2.引脚IO 接口
1. YIN[7..0]/CCDIN[7..0]
2. CIN[5..0]/CCDIN[13..0]
3.PCLK
4.CAM_HD,CAM_VD
5.CAM_WEN_FIELD:/设 CCD Write Enable/Field ID signal
1）作FIELD标识信号，FLDMODE定类型提供，由CCD/CMOSFIDMD/FLDPOL
2）作WEN用，EXWEN打开，WENLOG设定AND 或 OR，与在SPH, NPH, SLV, NLV内的有效像素相AND或OR
RAM模式引脚:
以上全需用到
另少于14BIT时,一般用CCD[13..0]高位,舍去底位,当用时SPI时除外
----------------------------------------------------------------
引脚配置REG: PINMUX0(VPFE.PDF PAGE38)
3。VPFE/ISP Integration
VPSS Events:9个作为中断送ARM，4个作为EVENT送EDMA
Number Acronym Module Description
0 CCDC VDINT0 CCDC Triggered after a programmable number of input lines for each frame.
1 CCDC VDINT1 CCDC Triggered after a programmable number of input lines for each frame.
2 CCDC VDINT2 CCDC Triggered at the rising edge of WEN signal
3 H3AINT H3A Triggered at the end of AF or AEW writes to DDR for each frame
4 VENCINT VENC Triggered at the rising edge of VSYNC
5 OSDINT OSD Triggered at the end of each frame read from DDR
6 IPIPEIFINT IPIPEIF Triggered at the rising edge of VD if enabled
7 IPIPE_INT0_HST IPIPE Triggered when Histogram processing is finished for each frame
8 IPIPE_INT1_SDR IPIPE Triggered when writes to DDR are finished for each frame
9 IPIPE_INT2_RZA IPIPE Triggered when the number of lines programmed has been output of RZA
10 IPIPE_INT3_RZB IPIPE Triggered when the number of lines programmed has been output of RZB
12 IPIPE_INT5_MMR IPIPE Triggered when MMR modifications for the next frame can be made
中断：VPSSBL.INTSEL选择
INT Number Acronym
0 VPSSINT0
1 VPSSINT1
2 VPSSINT2
3 VPSSINT3
4 VPSSINT4
5 VPSSINT5
6 VPSSINT6
7 VPSSINT7
8 VPSSINT8
事件：VPSSBL.EVTSEL选择
Event Number Binary Event Name
4 0000100 VPSSEVT1
5 0000101 VPSSEVT2
6 0000110 VPSSEVT3
7 0000111 VPSSEVT4
VPSS REG：
VPFE Module Register Map
VPSS Registers Address Range Size
VPSSCLK 0x01C70000 0x01C7007F 128B
H3A 0x01C70080 0x01C700FF 128B
IPIPEIF 0x01C70100 0x01C701FF 256B
OSD 0x01C70200 0x01C702FF 256B
VENC 0x01C70400 0x01C705FF 512B
CCDC 0x01C70600 0x01C707FF 512B
VPSSBL 0x01C70800 0x01C708FF 256B
IPIPE 0x01C71000 0x01C73FFF 12K-
-------------------------------------------------------------------------
4 。VPFE/ISP Functional Description
4.1 CCDC
参数：MODESET.INPMOD输出到DDR的数据选择，YCBCR或RGB
RAW模式时序参数：HDW，VDW，PPLN，HLPFR （从AFE来）
RAW模式时CCDCFG.YCINSWP=0
4.1.2.1 DIGITAL CLAMP
CLAMP的黑电平可用常量也可从像素中计算得到,也可从CCD SENSOR的上黑边，左黑边提取基量
以求平均值计算。
参数：CLAMP.OBST 黑像素开始点；CLAMP.OBSLEN每行的用来求平均的像素数；DCSUB.OBSLN求平均的行数
4.1.2.2 Color Space Conversion
CSCCTL[0]开启。由乘加器，LINE MEMORY组成，CMYG--》RGBG
FMTSPH, FMTLNH, FMTSLV, and FMTLNV指定数据区域
转换后数据会有一行LATENCY（延迟）。
最后一行至少要有一无效像素，一FRAME中至少要有一无效行
4.1.2.3 Defect Correction：坏点校正
DFCCTL[0]开启，可校正1024个点
4.1.2.4 Lens Shading Correction：镜头阴影校正
LSCCFG[0]开启，由于镜头中心较亮，向边缘渐暗。由此而校正
4.1.2.5 Black Level Compensation：太亮，太暗补偿
BLKCMP0.R_YE, BLKCMP0.GR_CY, BLKCMP1.GB_G, BLKCMP1.B_MG)
4.1.2.6 Median Filter：中央滤波。一路送SDRAM，另一路送IPIPE，可单独能动
1. Average Filter Configuration
2. Median Filter Configuration
GAMMAWD.MFILT1 and GAMMAWD.MFILT2
4.1.2.7 SDRAM RAW Output Formatting
4.1.4 Data Output Control
• SDOFST.FIINV – invert interpretation of the Field ID signal
• SDOFST.FIINV – invert interpretation of the Field ID signal
• SDOFST.LOFTS0 – offset, in lines, between even lines on even fields (field 0)
• SDOFST.LOFTS1 – offset, in lines, between odd lines on even fields (field 0)
• SDOFST.LOFTS2 – offset, in lines, between even lines on odd fields (field 1)
• SDOFST.LOFTS3 – offset, in lines, between odd lines on odd fields (field 1)
4.2 IPIPEIF
参数：HDW=8PIXEL，VDW=4LINE（CONTINUE）OR 10LINE（ONE SHOT），PPLN=HD 间隔，LPFR=VD 间隔>1 LINE，HNUM=水平有效像素（从HD上升沿开始？？？），VNUM=垂直有效像素（从VD下降沿开始，即隔4或10LINE）
4.2.1.1 CCDC RAW Input Mode (CFG.INPSRC = 0)
14BIT
4.2.1.2 SDRAM RAW Input Mode (CFG.INPSRC = 1h)
从SDRAM中读取8BIT或16BIT，8BIT为经过A-LAW压缩的，可设CFG.IALAW解压，也可填0补齐
4.2.1.3 CCDC RAW Input With Dark Frame Subtract From SDRAM Mode (CFG.INPSRC = 2h)
IPIPEIF INPUT = CCDC RAW INPUT - SDRAM INPUT
此时PPLN，LPFR的意义与其它输入模式不同，表示从CCDC DATA中减去时的水平，垂直方向的起始位置
4.2.1.4 SDRAM YCbCr 4:2:2 Input Mode (CFG.INPSRC = 3h)
16BIT YCbCr 4:2:2 data
4.2.2 时序产生
当输入为0或2时，HD/VD/WEN ，PCLK由CCDC提供， 为1或3时，IPIEIF产生HD/VD（基于LPFR and PPLN），PCLK可继续用CCDC的PCLK（CFG.CLKSEL=0），也可自已产生（CFG.CLKSEL=1）（用VPSSCLK分频CFG.CLKDIV），产生PCLK时要考虑下面IPIPE RESIZE时最大时钟要求及SDRAM实时操作要求
当CFG.INPSRC非0时，IPIPE I/F SDRAM data读及时序产生即可在ONE-SHOT 下，也可在CONTINUE模式下（(ENABLE.ENABLE）
当输入大于1344PIXEL时开启CFG.DECM设定比例系数以缩小到1344以下
4.3 IPIPE
参数：IPIPE_HST,IPIPE_VST定义开始点（与HD，VD上升沿为原点），IPIPE_HSZ, IPIPE_VSZ定义要处理的数据区域大小
IPIPE_COLPAT定义处理数据的Color pattern
Input Modes (IPIPE_DPATHS.FMT)
0: RAW to YCbCr
1: RAW to RAW
2: RAW to Boxcar
3: YCbCr to YCbCr
In RAW pass through mode,可以支持最大4096PIXEL/LINE，直接写到SDRAM
4.3.3 Defect Correction
4.3.4 Noise Filter
4.3.5 Pre Filter
为了减少LINE-CRAWLING，只针对green pixels.有两种方式（PRE_TYP选择）：1.常量 2.算法
4.3.6 White Balance
白平衡就是调整增益，有两种：
1.Digital gain调整影像总亮度，x 0 – x 3.996 (step = 1/256)
2. white balance gains 调整CFA中每个分量的增益，x 0 – x 7.992 (step = 1/128)
4.3.7 CFA Interpolation
由 Bayer RGB转换成RGB 4:4:4 data
4.3.8 RGB2RGB Blending（混合）
RGB混合，即增加一OFFSET，调成人类的色彩光谱。(RGB_MUL_[R,G,B][R,G,B], & RGB_OFT_[R,G,B])
4.3.9 Gamma Correction Module
摄像时亮度与电压成非线性关系，称此为GAMMA曲线，GAMMA校正即是校正此非线性
有三个通路：1.BYPASS 2. 从RAM TABLE 3. 从ROM TABLE
4.3.10 RGB2YCbCr Conversion Module
YCC_MUL_[R,G,B][Y,CB,CR], and YCC_OFT_[Y,CB,CR]
4.3.11 4:2:2 Conversion Module
转换成YCBCR422格式
4.3.12 2-D Edge Enhancer
针对亮度信号，提高IMAGE质量。YEE_EN.EN开启。用一高通FILER来获取图像边缘，FILER系数可编程(YEE_MUL_[0,1,2][0,1,2])，输出可下SHIFT（YEE_SHF.SHF）。增加RAM表值可加强sharpness
4.3.13 Median NR
用来减少边缘强度的pseudo peak（假峰值），YEE_EMF.EN开启
4.3.14 Chrominance Suppression
FCS_EN.EN开启。在图像的亮度很强区域，可能会有一两个色彩通道饱和，但其它色彩没有，这样就会造成假色彩，如最常出现的就是原本是白色的却出现的是粉红色， 色度抑制可减少假色彩。
4.3.15 Horizontal and Vertical Resize Module
范围： x1/16 scale-down to x8
参数：RSZ[n].RSZ_H_TYP类型选择，HRSZ (RSZ[n].RSZ_H_DIF) and VRSZ (RSZ[n].RSZ_V_DIF)比例，上下限为32-4096，对应X8-X1/16，实际以256/HRSZ，256/VRSZ计算，影像输出尺寸最大为1344 pixels/line for RSZ[0] and 640 pixels/line for RSZ[1].
Vertical resize有两种模式：输入行号模式（RSZ_SEQ.TMM = 1)，连续模式。RSZ[n].RSZ_V_PHS_O定义最后输出位置
4.3.16 Output Interface
YCC_Y_MAX, YCC_Y_MIN, YCC_C_MAX, and YCC_C_MIN 定义Y，C大小范围，YCBCR422 TO YCBCR444，TO RGB，输出32BIT
4.3.17 RGB Converter
在H/V RESIZER中，YCBCR422通过线性插值，转成YCBCR444，由于此关系，第一行的一前一后两个像素会丢失，即RESIZE后会比想要的少两个像素。
在SDRAM BURST（256BIT）时以数据打包方式访问，有两种打包方式，32BIT，16BIT，(RSZ[n].RGB_TYP.TYP选择。32BIT时输出RGB各8位，及8BIT alpha value(在RSZ[n].RGB_BLD设定）；In 16-bit mode, R (5-bit), G (6-bit), and B (5-bit)输入到SDRAM。
4.4 H3A
5 Programming Model
VPFE Memory Master Selection
Shared Memory Register Field Settings
Shared Read Buffer (SRB) PCR.RBLCTRL 0: IPIPEIF
1: Reserved
2: H3A
Shared Write Buffer (SWB) PCR.WBLCTRL 0: IPIPEIF
1: Reserved
DFC Table MEMCTRL.DFCCTRL 0: IPIPE
1: CCDC
RSZ Line Memory MEMCTRL.RSZ_CTRL 0: IPIPEIF
1: Reserved
5.4 编程CCDC
模块能动：SYNCEN.VDHDEN能动CCDC，在能动之前需先设置一些REG。
SYNCEN.WEN 写SDRAM能动
若CCDC为MASTER MODE，则当SYNCEN.VDHDEN 后立即进行数据处理
若CCDC为SLAVE MODE, 则 SYNCEN.VDHDEN 应先于外部设备打开,以免数据丢失
设置顺序:
1. Set Data output address (STADRH & STADRL).
2. Enable HD/VD and WEN at the same time (MODESET.WEN & SYNCEN.VDHDEN)
中断:
VDINT0, VDINT1, and VDINT2
VDINT0,VDINT1达到VDINT.VDINT0 and VDINT.VDINT1中的行数后中断
VDINT2 以 CAM_WEN_FIELD为参考,在下降沿中断
MODESET.FLDSTAT场状态指示
REG整体上可分两种：
Shadowed Registers (event latched registers)—可随时读写，但只有当一定的事件发生时才起作用
Busy-Writeable Registers—可随时读写，即时发生作用
5.5 Programming the Image Pipe Interface (IPIPEIF)
模块能动：ENABLE.ENABLE ，当输入为CCDC RAW时，不需能动，CCDC 送什么就处理什么
当输入为SDRAM时CFG.ONESHOT定义ONESHOT模式还是CONTINOUS模式。在ONESHOT模式，只有一FRAME被处理，且ENABLE.ENABLE自动清0
会产生一 IPIPEIF event to the VPSSBL
5.6 Programming the Image Pipe (IPIPE)
模块能动：IPIPE_EN.EN
IPIPE EVENT
IRQ0 Final pixel from each frame is flushed from the image pipe (not resizer) and histogram completion event
IRQ1 SDRAM Write Completion Event
IRQ2 RZA Interval Completion Event
IRQ3 RZB Interval Completion Event
IRQ5 Register Update Ready Notification Event
5.6.1.2.1 Resizer Bypass Mode
Since the YCbCr data still passes through the RZA block in resizer bypass mode, the following registers
must be set accordingly:
GCK_SDR = 0 RSZ[0].RSZ_V_DIF = 256
RSZ_SEQ.SEQ = 0 RSZ[0].RSZ_H_PHS = 0
RSZ_SEQ.TMM = 0 RSZ[0].RSZ_H_DIF = 256
RSZ_AAL = 0 RSZ[0].RSZ_H_LSE = 0
RSZ[0].RSZ_O_HPS = 0 RSZ[1].RSZ_EN = 0
RSZ[0].RSZ_V_PHS = 0
5.6.1.2.2 RAW input, RAW output Mode (IPIPE_DPATHS.FMT = 1)
In this mode, the RAW data bypasses the RAW to YCbCr processes (see Figure 37), but since it still
passes through the YCbCr processing blocks, the following registers must be set accordingly:
IPIPE_DPATHS.FMT = 1 YEE_EN = 0 RSZ[0].RSZ_V_DIF = 256
BOX_EN = 0 FCS_EN = 0 RSZ[0].RSZ_H_PHS = 0
YCC_ADJ.CTR = 16 RSZ_SEQ.TMM = 0 RSZ[0].RSZ_H_DIF = 256
YCC_ADJ.BRT = 0 RSZ[0].RSZ_EN = 1 RSZ[0].RSZ_H_TYP = 0
YCC_Y_MIN = 0 RSZ[0].RSZ_I_VPS = 0 RSZ[0].RSZ_H_LSE = 0
YCC_Y_MAX = 255 RSZ[0].RSZ_I_HPS = 0 RSZ[0].RSZ_H_LPF = 0
YCC_C_MIN = 0 RSZ[0].RSZ_O_HPS = 0 RSZ[0].RSZ_RGB_EN = 0
YCC_C_MAX = 255 RSZ[0].RSZ_V_PHS = 0 RSZ[1].RSZ_EN = 0
5.6.1.3.1 Read/Write Procedures
The IPIPE internal memory values can be written, read, and written after read. If multiple values need to
be set in incremental addresses, then the RAM_MODE.ADR bit can be set so that only the first address
needs to be set and subsequent reads/writes will auto-increment the internal address. The following
procedures should be followed to access the internal memories:
For memory write:
1. Write to RAM_MODE: set memory selection and set EXT = 0 andWDT = 1.
2. Write to RAM_ADR: set starting offset into memory.
3. Write to RAM_WDT: Write data.
For memory read:
1. Write to RAM_MODE: set memory selection and set EXT = 0 andWDT = 0.
2. Write to RAM_ADR: set starting offset into memory.
3. Write to RAM_WDT: Write dummy data.
4. Read the data of the internal memory from RAM_RDT.
For memory write after read:
1. Write to RAM_MODE: set memory selection and set EXT = 0 andWDT = 1.
2. Write to RAM_ADR: set starting offset into memory.
3. Write to RAM_WDT: Write data.
4. Read the data of the internal memory from RAM_RDT.
5.7 Programming the Hardware 3A (H3A)
模块能动： PCR.AF_EN ，PCR.AEW_EN
当输入为SDRAM时，ONE-SHOT模式处理.若要处理每FRAME,则需设定PCR.SDR_FETCH_EN
当输入为CCDC时, CONTINUOUS模式处理,此时依据CCDC的时序来处理.应先CCDC能动
此模块处理完一FRAME后,可产生一中断和一EVENT
5.8 Programming the Buffer Logic (VPSSBL and VPSSCLK Registers)
VPSSBL and VPSSCLK Required Configuration Parameters
Function Configuration Required
CCDC VPSSBL.MEMCTRL.DFCCTRL
VPSSCLK.CLKCTRL.CCDCCLK
IPIPEIF VPSSBL.PCR.RBLCTRL
VPSSCLK.CLKCTRL.IPIPECLK
IPIPE VPSSBL.PCR.WBLCTRL
VPSSBL.MEMCTRL.IPIPE_WD_EN
VPSSBL.MEMCTRL.RESZ_CTRL
VPSSBL.MEMCTRL.DFCCTRL
VPSSCLK.CLKCTRL.IPIPECLK
H3A VPSSBL.PCR.RBLCTRL
VPSSCLK.CLKCTRL.H3ACLK
中断及事件选择VPSSBL.INTSEL and VPSSBL.EVTSEL
DM355 Reset Types
Type Initiator Effect
POR (Power-On-Reset) RESETN pin low and TRSTN low Total reset of the chip (cold reset). Resets all modules including memory and emulation.
Warm Reset RESETN pin low and TRSTN high (initiated by Resets all modules including memory, except ARM
ARM emulator). emulation.
Max Reset ARM emulator or Watchdog Timer (WDT). Same effect as warm reset.
System Reset ARM emulator Resets all modules except memory and ARM
emulation. It is a soft reset that maintains memory contents and does not affect or reset clocks or power states.
Module Reset ARM software Resets a specific module. Allows the ARM software
to independently reset a module. Module reset is intended as a debug tool not as a tool to use in production.
POR (Power-On-Reset) RESETN pin low and TRSTN low Total reset of the chip (cold reset). Resets all modules including memory and emulation.
Warm Reset RESETN pin low and TRSTN high (initiated by Resets all modules including memory, except ARM
ARM emulator). emulation.
Max Reset ARM emulator or Watchdog Timer (WDT). Same effect as warm reset.
System Reset ARM emulator Resets all modules except memory and ARM
emulation. It is a soft reset that maintains memory contents and does not affect or reset clocks or power states.
Module Reset ARM software Resets a specific module. Allows the ARM software
to independently reset a module. Module reset is intended as a debug tool not as a tool to use in production.
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