DM355 ARM SUBSYSTEM

3.1 DM355 ARM：

· ARM926EJ-S - 32-bit RISC processor
· 16-KB Instruction cache
· 8-KB Data cache
· MMU
· CP15 to control MMU, cache, write buffer, etc.
· Java accelerator
· ARM Internal Memory
– 32-KB built-in RAM
– 8-KB built-in ROM (boot ROM)
· Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
· Features:
– The main write buffer has a 16-word data buffer and a 4-address buffer
– Support for 32/16-bit instruction sets
– Fixed little endian memory format
– Enhanced DSP instructions

3.2 Operating States/Modes

· User mode (USR): Non-privileged mode, usually for the execution of most
application programs.
· Fast interrupt mode (FIQ): Fast interrupt processing
· Interrupt mode (IRQ): Normal interrupt processing
· Supervisor mode (SVC): Protected mode of execution for operating systems
· Abort mode (ABT): Mode of execution after a data abort or a pre-fetch
abort
· System mode (SYS): Privileged mode of execution for operating systems
· Undefined mode (UND): Executing an undefined instruction causes the ARM
to enter undefined mode.

可以从其它MODE进入privileged modes (system or supervisor)，如从USER
MODE要进入privileged modes 可以发出软件中断（SWI），IRQ或FIQ来进行

不同的模式需设置不同的STACK，STACK POINT自动指到其模式的SP

3.3 Processor Status Registers

processor status register
(PSR)设置中断能动禁止，操作模式设置。PSR[7：0]控制位，PSR[27：8]保留，PSR
[31:28]状态位。PSR[7:0]如下：

· Bit 7 - I bit: Disable IRQ (I =1) or enable IRQ (I = 0)
· Bit 6 - F bit: Disable FIQ (F = 1) or enable FIQ (F = 0)
· Bit 5 - T bit: Controls whether the processor is in thumb mode (T = 1)
or ARM mode (T = 0)
· Bits 4:0 Mode: Controls the mode of operation of the processor
– PSR [4:0] = 10000 : User mode
– PSR [4:0] = 10001 : FIQ mode
– PSR [4:0] = 10010 : IRQ mode
– PSR [4:0] = 10011 : Supervisor mode
– PSR [4:0] = 10111 : Abort mode
– PSR [4:0] = 11011 : Undefined mode
– PSR [4:0] = 11111 : System mode

PSR[31:28]反映算术单员ALU的状态：

· Bit 31 - N bit: Negative or less than
· Bit 30 - Z bit: Zero
· Bit 29 - C bit: Carry or borrow
· Bit 28 - V bit: Overflow or underflow

3.4 Exceptions and Exception Vectors例外及其向量

例外可有以下方式产生

· Reset exception: processor reset
· FIQ interrupt: fast interrupt
· IRQ interrupt: normal interrupt
· Abort exception: abort indicates that the current memory access could
not be completed. The abort
could be a pre-fetch abort or a data abort.
· SWI interrupt: use software interrupt to enter supervisor mode.
· Undefined exception: occurs when the processor executes an undefined
instruction

以上由高到低优先权为：reset, data abort, FIQ, IRQ, pre-fetch
abort, undefined instruction及SWI，undefined instruction及SWI优先权一样。

依靠CP15寄存器中VINTH来设置向量表位置：0x00000000 (VINTH = 0) or at
address 0xFFFF0000 (VINTH = 1). .

注： 以上只是ARM926EJ-S
core的特性，在DMSOC中，0xFFFF0000处没有内存，所以并不设置VINTH

Table 3-1. Exception Vector Table for ARM
Vector Offset Address Exception Mode on entry I Bit State
on Entry F Bit State on Entry
0h Reset Supervisor
Set Set
04h fined instruction Undefined
Set Unchanged
08h Software interrupt Supervisor
Set Unchanged
0Ch Pre-fetch abort Abort
Set Unchanged
10h Data abort Abort
Set Unchanged
14h Reserved -
- -
18h IRQ IRQ
Set Unchanged
1Ch FIQ FIQ
Set Set

3.5 The 16-BIS/32-BIS Concept

16位指令集是32位的缩减，相同条件下，16位的代码是32位的65%，当连接16
MEMORY进其性能是32位的1.6倍

3.6 Coprocessor 15 (CP15)

system control coprocessor
(CP15)用来设置指令及数据caches，Tightly-Coupled Memories (TCMs), Memory
Management Units (MMUs), and many system functions。CP15寄存器仅能由MRC
and MCR

指令在privileged mode下访问。

3.6.1 Addresses in an ARM926EJ-S System

Different Address Types in ARM Syste

Domain ARM9EJ-S Caches and MMU
TCM and AMBA Bus
Address type Virtual Address (VA) Modified Virtual Address (MVA) P
hysical Address (PA)

The VA of the instruction is issued by the ARM9EJ-S core.
The VA is translated to the MVA. The Instruction Cache (Icache) and Memory
Management Unit (MMU)
detect the MVA.
If the protection check carried out by the MMU on the MVA does not abort
and the MVA tag is in the
Icache, the instruction data is returned to the ARM9EJ-S core.
If the protection check carried out by the MMU on the MVA does not abort,
and the MVA tag is not in
the cache, then the MMU translates the MVA to produce the PA.

3.6.2 Memory Management Unit

3.6.3 Caches and Write Buffer

· An Instruction cache (Icache) 16KB
· A Data cache (Dcache) 8KB
· A write buffer 17 bytes

3.7 Tightly Coupled Memory

TCM主要用来作实时及关键代码

DM355 supports both instruction TCM (I-TCM) and data TCM (D-TCM). The
instruction TCM is located at
0x0000:0000 to 0x0000:7FFF. The data TCM is located at 0x0001:0000 to
0x0001:9FFF

--------------------------------------------------------------------------------------

ITCM/DTCM Memory Map
I-TCM Address D-TCM Address Size
(Bytes) Description
0x0000 :0000 - 0x0000 :3FFF 0x0001 :0000 - 0x0001 :3FFF
16K IRAM0
0x0000 :4000 - 0x0000 :7FFF 0x0001 :4000 - 0x0001 :7FFF
16K IRAM1
0x0000 :8000 - 0x0000 :9FFF 0x0001 :8000 - 0x0001 :9FFF
8K ROM
0x0000 :A000 - 0x0000 :FFFF 0x0001 :A000 - 0x0001 :FFFF
24K Reserved

------------------------------------------------------------------------------------------

TCM状态可从CP15 reg 0读取

TCM状态寄存器

31
17 16

SBZ/UNP
DTCM

15
1 0
SBZ/UNP
ITCM

------------------------------------------------------------------------------------------

TCM数据寄存器

31
16
ADDRESS
15 12 11 6 5
2 1 0
ADDRESS S BZ/UNP
SIZE 0 ENB

----------------------------------------------------------------------------------------

ITCM/DTCM Size Encoding
Binary Code Size
0000 0 KB / absent
0001,0010 Reserved
0011 4 KB
0100 8 KB
0101 16 KB
0110 32 KB
0111 64 KB
1000 128 KB
1001 256 KB
1010 512 KB
1011 1 MB
11xx Reserved

注：

用0x00010019 to enable DTCM for DM355: 0x00010000 (base address) |
0b0110 << 2 (size) | 1 (enable)

3.8 Embedded Trace Support

Embedded Trace Macrocell (ETM),Embedded Trace Buffer (ETB).

注：The DM355 trace port is not pinned out. Instead, it is connected to a
4KB Embedded Trace
Buffer. ETB enabled debug tools are required to read/interpret the
captured trace data.

Trace Port Analyzer (TPA)

ETM Part Descriptions
ETM Part Descriptions
Trace Port: The trace port allows you to debug the
PRocessor.

The trace port has a protocol that has been
developed to provide a real-time trace
capability for processor cores that are deeply embedded in
large ASIC designs. This is beneficial to developers
and manufacturers when it is not possible to
determine how the processor core is operating by only observing the pins
of the ASIC.
Triggering Facilities:

An extensible ETM specification exists to specify the exact set of trigger
resources required for a
particular application. Resources include address and data comparators,
counters, and
sequencers.