4.1 Memory Map
Table 4-1. DM355 Memory Map
Start Address End Address Size (Bytes) ARM
EDMA USB VPSS
Mem Map Mem Map
Mem Map Mem Map
0x0000 0000 0x0000 3FFF 16K ARM RAM0
(Instruction)
----------------------------------------------------------------------------------------------
0x0000 0000 0x00007FFF 16K ARMRAM1 Reserved
Reserved
(Instruction)
----------------------------------------------------------------------------------------------
0x0000 8000 0x0000 FFFF 32K ARM ROM
(Instruction)
- only 8K used
----------------------------------------------------------------------------------------------
0x0001 0000 0x0001 3FFF 16K ARM RAM0 (Data) ARM
RAM0 ARM RAM0
----------------------------------------------------------------------------------------------
0x0001 4000 0x0001 7FFF 16K ARM RAM1 (Data) ARM
RAM1 ARM RAM1
----------------------------------------------------------------------------------------------
0x0001 8000 0x0001 FFFF 32K ARM ROM (Data) ARM
ROM ARM ROM
- only 8K used
----------------------------------------------------------------------------------------------
0x0002 0000 0x000F FFFF 896K Reserved
----------------------------------------------------------------------------------------------
0x0010 0000 0x01BB FFFF 26M
----------------------------------------------------------------------------------------------
0x01BC 0000 0x01BC 0FFF 4K ARM ETB Mem
----------------------------------------------------------------------------------------------
0x01BC 1000 0x01BC 17FF 2K ARM ETB Reg Reserved
----------------------------------------------------------------------------------------------
0x01BC 1800 0x01BC 18FF 256 ARM IceCrusher Reserved
----------------------------------------------------------------------------------------------
0x01BC 1900 0x01BC FFFF 59136 Reserved
----------------------------------------------------------------------------------------------
0x01BD 0000 0x01BF FFFF 192K
----------------------------------------------------------------------------------------------
0x01C0 0000 0x01FF FFFF 4M CFGBus CFG
Bus Reserved
Peripherals Peripherals
----------------------------------------------------------------------------------------------
0x0200 0000 0x09FF FFFF 128M ASYNC EMIF ASYNC EMIF
(Data) (Data)
----------------------------------------------------------------------------------------------
0x0A00 0000 0x11EF FFFF 127M - 16K
----------------------------------------------------------------------------------------------
0x11F0 0000 0x11F1 FFFF 128K Reserved Reserved
----------------------------------------------------------------------------------------------
0x11F2 0000 0x1FFF FFFF 141M-64K
----------------------------------------------------------------------------------------------
0x2000 0000 0x2000 7FFF 32K DDR EMIF Control DDR EMIF
Control
Regs Regs
----------------------------------------------------------------------------------------------
0x2000 8000 0x41FF FFFF 544M-32K Reserved
----------------------------------------------------------------------------------------------
0x4200 0000 0x49FF FFFF 128M Reserved AEMIF -
shadow
----------------------------------------------------------------------------------------------
0x4A00 0000 0x7FFF FFFF 864M Reserved
----------------------------------------------------------------------------------------------
0x8000 0000 0x8FFF FFFF 256M DDR EMIF DDR EMIF
DDR EMIF DDR EMIF
----------------------------------------------------------------------------------------------
0x9000 0000 0xFFFF FFFF 1792M Reserved Reserved
Reserved Reserved
4.1.1 ARM Internal Memories
32KB ARM Internal RAM（与TCM接口）可分成2PAGE
8KB ARM Internal ROM
注：ARM access to internal memory is with one wait-state.当ARM
频率少于或等于150M时可设置zero wait-state，用Miscellaneous Control
register (MISC）之AIM_WAIST来设置
4.1.2 External Memories
· DDR2 / mDDR Synchronous DRAM
· Asynchronous EMIF/OneNand
· NAND Flash
· External Host Devices
此外还可访问各种多媒存储接口
4.1.3 MPEG/JPEG Coprocessor (MJCP)
4.1.4 Peripherals
ARM和EDMA可访问以下外部设备
· EDMA Controller
· Three UARTs
· I2C (Inter-IC Communication)
· Three 64-bit timers (each configurable as one 64-bit timer or two 32 bit
timers) and one WDT
· PWM (Pulse Width Modulator)
· USB (Universal Serial Bus Controller)
· Three SPI serial interfaces
· General-Purpose Input/Output (GPIO)
· Video Processing Subsystem (VPSS)
· Asynchronous EMIF (AEMIF) Controller
· Real Time Out (RTO)
也可访问以下内部设置
· ETM/ETB
· ICEcrusher
· System Module
· PLL Controllers
· Power Sleep Controller
· ARM Interrupt Controller
DM355 ARM Configuration Bus Access to Peripherals
Address
Accessibility
Region Start End
Size ARM EDMA
EDMA CC 0x01C0 0000 0x01C0 FFFF 64K
EDMA TC0 0x01C1 0000 0x01C1 03FF 1K
EDMA TC1 0x01C1 0400 0x01C1 07FF 1K
Reserved 0x01C1 8800 0x01C1 9FFF 6K
Reserved 0x01C1 A000 0x01C1 FFFF 24K
UART0 0x01C2 0000 0x01C2 03FF 1K
UART1 0x01C2 0400 0x01C2 07FF 1K
Timer4/5 0x01C2 0800 0x01C2 0BFF 1K
Real-time out 0x01C2 0C00 0x01C2 0FFF 1K
I2C 0x01C2 1000 0x01C2 13FF 1K
Timer0/1 0x01C2 1400 0x01C2 17FF 1K
Timer2/3 0x01C2 1800 0x01C2 1BFF 1K
WatchDog Timer 0x01C2 1C00 0x01C2 1FFF 1K
PWM0 0x01C2 2000 0x01C2 23FF 1K
PWM1 0x01C2 2400 0x01C2 27FF 1K
PWM2 0x01C2 2800 0x01C2 2BFF 1K
PWM3 0x01C2 2C00 0x01C2 2FFF 1K
System Module 0x01C4 0000 0x01C4 07FF 2K
PLL Controller 0 0x01C4 0800 0x01C4 0BFF 1K
PLL Controller 1 0x01C4 0C00 0x01C4 0FFF 1K
Power/Sleep Controller 0x01C4 1000 0x01C4 1FFF 4K
ARM Interrupt Controller 0x01C4 8000 0x01C4 83FF 1K
USB OTG 2.0 Regs / RAM 0x01C6 4000 0x01C6 5FFF 8K
SPI0 0x01C6 6000 0x01C6 67FF 2K
SPI1 0x01C6 6800 0x01C6 6FFF 2K
GPIO 0x01C6 7000 0x01C6 77FF 2K
SPI2 0x01C6 7800 0x01C6 FFFF 2K
VPSS Subsystem 0x01C7 0000 0x01C7 FFFF 64K
VPSS Clock Control 0x01C7 0000 0x01C7 007F 128
Hardware 3A 0x01C7 0080 0x01C7 00FF 128
Image Pipe (IPIPE) 0x01C7 0100 0x01C7 01FF 256
Interface
On Screen Display 0x01C7 0200 0x01C7 02FF 256
High Speed Serial IF 0x01C7 0300 0x01C7 03FF 256
Video Encoder 0x01C7 0400 0x01C7 05FF 512
CCD Controller 0x01C7 0600 0x01C7 07FF 256
VPSS Buffer Logic 0x01C7 0800 0x01C7 08FF 256
CFA Multiply Mask / Lens 0x01C7 0900 0x01C7 09FF 256
Distortion
Image Pipe (IPIPE) 0x01C7 1000 0x01C7 3FFF 12K
Reserved 0x01CC 0000 0x01CD FFFF 128K
Reserved 0x01CD 0000 0x01CD 007F 128
Reserved 0x01CD 0380 0x01CD 03FF 128
Reserved 0x01CD F400 0x01CD F4FF 256
Sequencer 0x01CD FF00 0x01CD FFFF 256
Multimedia / SD 1 0x01E0 0000 0x01E0 1FFF 8K
ASP0 0x01E0 2000 0x01E0 3FFF 8K
ASP1 0x01E0 4000 0x01E0 5FFF 8K
UART2 0x01E0 6000 0x01E0 63FF 1K
Reserved 0x01E0 6400 0x01E0 FFFF 39K
ASYNC EMIF Control 0x01E1 0000 0x01E1 0FFF 4K
Multimedia / SD 0 0x01E1 1000 0x01E1 FFFF 60K
Reserved 0x01E2 0000 0x01FF FFFF 1792K
ASYNC EMIF Data (CE0) 0x0200 0000 0x03FF FFFF 32M
ASYNC EMIF Data (CE1) 0x0400 0000 0x05FF FFFF 32M
Reserved 0x0A00 0000 0x0BFF FFFF 32M
Reserved 0x0C00 0000 0x0FFF FFFF 64M
4.2 Memory Interfaces Overview
4.2.1 DDR2 EMIF 只支持16位BUS
· Buffering input image data from sensors or video sources,
· Intermediate buffering for processing/resizing of image data in the VPFE,
· Numerous OSD display buffers
· Intermediate buffering for large raw Bayer data image files while
performing still camera processing
functions
· Buffering for intermediate data while performing video encode and decode
functions
· Storage of executable firmware for the ARM
· etc.
4.2.2 External Memory Interface
· Asynchronous memories (SRAM, Linear flash, etc.)
· NAND flash memories
· OneNAND flash memories
4.2.2.1 Asynchronous EMIF (AEMIF)
· SRAM on up to two asynchronous chip selects
· Supports 8-bit or 16-bit data bus widths
· Programmable asynchronous cycle timings
· Supports extended waits
· Supports Select Strobe mode
· Supports booting DM355's ARM processor from CE0 (e.g SRAM) via direct
execution
SPRUFB3–
4.2.2.2 NAND (NAND, SmartMedia, xD)
The NAND mode supports the following features:
· NAND Flash on up to two asynchronous chip selects
· Supports 8-bit and 16-bit data bus widths
· Programmable cycle timings
· Performs 1-bit and 4-bit ECC calculation (does not perform error
correction)
· NAND Mode also supports SmartMedia/SSFDC (Solid State Floppy Disk
Controller) and xD memory
cards
· ARM ROM supports booting of DM355's ARM processor from NAND-Flash
located at CE0
4.2.2.3 OneNAND
The OneNAND mode supports the following features:
· OneNAND Flash on up to two chip selects
· Supports only 16-bit data bus widths
· Supports asynchronous writes and reads
· Supports synchronous reads with continuous linear burst mode
· Does not support synchronous reads with wrap burst modes
· Programmable cycle timings for each chip select in asynchronous mode
· Supports booting of DM355's ARM processor from OneNAND-Flash located at
CE0 via direct
execution
34
5.1 Overview
5.2 Peripheral Clocking Considerations
5.2.1 Video Processing Back End Clocking
VPBE时钟分内部外部，内部用PLL1 之SYSCLK4
外部用：
· 24 MHz crystal input at MXI1
· 27 MHz crystal input at MXI2 (optional feature)
· PLL1 SYSCLK3
· EXTCLK pin (external VPBE clock input pin)
· PCLK pin (VPFE pixel clock input pin)
。。。。。。。。
6.6 PLL Controller Register Map
7.Power and Sleep Controller
Table 7-1. Module Configuration
Default States
Module Module Name Power Domain Power Domain State Module State
Number
0 VPSS Master AlwaysOn ON SyncRst
1 VPSS Slave AlwaysOn ON SyncRst
2 EDMA (CC) AlwaysOn ON BTSEL[1:0] = 00 – Enable (NAND)
BTSEL[1:0] = 01 – Enable (OneNAND)
3 EDMA (TC0) AlwaysOn ON BTSEL[1:0] = 10 – SyncRst (MMC/SD)
BTSEL[1:0] = 11 – Enable (UART)
4 EDMA (TC1) AlwaysOn ON SyncRst
5 TIMER3 AlwaysOn ON SyncRst
6 SPI1 AlwaysOn ON SyncRst
7 MMC/SD1 AlwaysOn ON SyncRst
8 ASP1 AlwaysOn ON SyncRst
9 USB AlwaysOn ON SyncRst
10 PWM3 AlwaysOn ON SyncRst
11 SPI2 AlwaysOn ON SyncRst
12 RTO AlwaysOn ON SyncRst
13 DDR EMIF AlwaysOn ON SyncRst
14 AEMIF AlwaysOn ON BTSEL[1:0] = 00 – Enable (NAND)
BTSEL[1:0] = 01 – Enable (OneNAND)
BTSEL[1:0] = 10 – SyncRst (MMC/SD)
BTSEL[1:0] = 11 – Enable (UART)
15 MMC/SD0 AlwaysOn ON BTSEL[1:0] = 00 – SyncRst (NAND)
BTSEL[1:0] = 01 – SyncRst (OneNAND)
BTSEL[1:0] = 10 – Enable (MMC/SD)
BTSEL[1:0] = 11 – SyncRst (UART)
16 MemStick AlwaysOn ON SyncRst
17 ASP0 AlwaysOn ON SyncRst
18 I2C AlwaysOn ON SyncRst
19 UART0 AlwaysOn ON BTSEL[1:0] = 00 – SyncRst (NAND)
BTSEL[1:0] = 01 – SyncRst (OneNAND)
BTSEL[1:0] = 10 – SyncRst (MMC/SD)
BTSEL[1:0] = 11 – Enable (UART)
20 UART1 AlwaysOn ON SyncRst
21 UART2 AlwaysOn ON SyncRst
22 SPI0 AlwaysOn ON SyncRst
23 PWM0 AlwaysOn ON SyncRst
24 PWM1 AlwaysOn ON SyncRst
25 PWM2 AlwaysOn ON SyncRst
26 GPIO AlwaysOn ON SyncRst
27 TIMER0 AlwaysOn ON BTSEL[1:0] = 00 – Enable (NAND)
BTSEL[1:0] = 01 – Enable (OneNAND)
BTSEL[1:0] = 10 – Enable (MMC/SD)
BTSEL[1:0] = 11 – Enable (UART)
28 TIMER1 AlwaysOn ON SyncRst
29 TIMER2 AlwaysOn ON Enable
30 System Module AlwaysOn ON Enable
31 ARM AlwaysOn ON Enable
32 BUS AlwaysOn ON Enable
33 BUS AlwaysOn ON Enable
34 BUS AlwaysOn ON Enable
35 Emulation AlwaysOn ON Enable
36 Test AlwaysOn ON Enable
37 Test AlwaysOn ON Enable
38 Test AlwaysOn ON Enable
39 Reserved Reserved Reserved Reserved
40 MPEG/JPEG AlwaysOn ON SyncRst
Coprocessor (MJCP)
41 VPSS DAC Always On ON SyncRst
7.3.2 Module States
A module can be in one of four states: Disable, Enable, SwRstDisable, or SyncReset.
7.4.2 Module State Transitions
· Wait for the GOSTATx bit in PTSTAT to clear to 0x0. You must wait for any previously initiated
transitions to finish before initiating a new transition.
· Set the NEXT bit in MDCTL[x] to SwRstDisable (0x0), SyncReset (0x1), Disable (0x2), or Enable (0x3).
Note: You may set transitions in multiple NEXT bits in MDCTL[x] in this step.
· Set the GOx bit in PTCMD to 0x1 to initiate the transition(s).
· Wait for the GOSTATx bit in PTSTAT to clear to 0x0. The module is only safely in the new state after
the GOSTATx bit in PTSTAT clears to 0x0.
AINTC Interrupt Connections
Interrupt Acronym Source Interrupt Acronym Source
Number Number
0 VPSSINT0 VPSS - INT0, 32 TINT0 Timer 0 - TINT12
Configurable via
VPSSBL register:
INTSEL
1 VPSSINT1 VPSS - INT1 33 TINT1 Timer 0 - TINT34
2 VPSSINT2 VPSS - INT2 34 TINT2 Timer 1 - TINT12
3 VPSSINT3 VPSS - INT3 35 TINT3 Timer 1 - TINT34
4 VPSSINT4 VPSS - INT4 36 PWMINT0 PWM0
5 VPSSINT5 VPSS - INT5 37 PWMINT1 PWM 1
6 VPSSINT6 VPSS - INT6 38 PWMINT2 PWM2
7 VPSSINT7 VPSS - INT7 39 I2CINT I2C
8 VPSSINT8 VPSS - INT8 40 UARTINT0 UART0
41 UARTINT1 UART1
9 - 11 Reserved for use 42 SPINT0-0 SPI0
with the MJCP
43 SPINT0-1 SPI0
12 USBINT USB OTG Collector 44 GPIO0 GPIO
13 RTOINT or RTO or 45 GPIO1 GPIO
TINT4 Timer 2 - TINT12
SYS.ARM_INTMUX
14 UARTINT2 or UART2 or 46 GPIO2 GPIO
TINT5 Timer 2 - TINT34
15 TINT6 Timer 3 TINT12 47 GPIO3 GPIO
16 CCINT0 EDMA CC Region 0 48 GPIO4 GPIO
17 SPINT1-0 or SPI1 or 49 GPIO5 GPIO
CCERRINT EDMA CC Error
18 SPINT1-1 or SPI1 or 50 GPIO6 GPIO
TCERRINT0 EDMA TC0 Error
19 SPINT2-0 or SPI2 or 51 GPIO7 GPIO
TCERRINT1 EDMA TC1 Error
20 PSCINT PSC - ALLINT 52 GPIO8 GPIO
21 SPINT2-1 SPI2 53 GPIO9 GPIO
22 TINT7 Timer3 - TINT34 54 GPIOBNK0 GPIO
23 SDIOINT0 SDIO0 55 GPIOBNK1 GPIO
24 MBXINT0 or ASP0 or 56 GPIOBNK2 GPIO
MBXINT1 ASP1
25 MBRINT0 or ASP0 or 57 GPIOBNK3 GPIO
MBRINT1 ASP1
26 MMCINT0 MMC/SD0 58 GPIOBNK4 GPIO
27 MMCINT1 MMC/SD1 59 GPIOBNK5 GPIO
28 PWMINT3 PWM3 60 GPIOBNK6 GPIO
29 DDRINT DDR EMIF 61 COMMTX ARMSS
30 AEMIFINT Async EMIF 62 COMMRX ARMSS
31 SDIOINT1 SDIO1 63 EMUINT E2ICE
8.3.3 Vector Table Entry Address Generation
IRQENTRY = EABASE + ((highest priority IRQ EVT# + 1) * SIZE)
FIQENTRY = EABASE + ((highest priority FIQ EVT# + 1) * SIZE)
8.4 INTC Registers
Interrupt Controller (INTC) Registers
Offset Acronym Register Description Section
00h FIQ0 Interrupt Status of INT [31:0] (if mapped to FIQ) Section 8.4.1
04h FIQ1 Interrupt Status of INT [63:32] (if mapped to FIQ) Section 8.4.2
08h IRQ0 Interrupt Status of INT [31:0] (if mapped to IRQ) Section 8.4.3
0Ch IRQ1 Interrupt Status of INT [63:32] (if mapped to IRQ) Section 8.4.4
10h FIQENTRY Entry Address [28:0] for valid FIQ interrupt Section 8.4.5
14h IRQENTRY Entry Address [28:0] for valid IRQ interrupt Section 8.4.6
18h EINT0 Interrupt Enable Register 0 Section 8.4.7
1Ch EINT1 Interrupt Enable Register 1 Section 8.4.8
20h INTCTL Interrupt Operation Control Register Section 8.4.9
24h EABASE Interrupt Entry Table Base Address Section 8.4.10
30h INTPRI0 Interrupt 0-7 Priority select Section 8.4.11
34h INTPRI1 Interrupt 8-15 Priority select Section 8.4.12
38h INTPRI2 Interrupt 16-23 Priority select Section 8.4.13
3Ch INTPRI3 Interrupt 24-31 Priority select Section 8.4.14
40h INTPRI4 Interrupt 32-29 Priority select Section 8.4.15
44h INTPRI5 Interrupt 40-47 Priority select Section 8.4.16
48h INTPRI6 Interrupt 48-55 Priority select Section 8.4.17
4Ch INTPRI7 Interrupt 56-63 Priority select Section 8.4.18
System Control Module
· Device Identification
· Device Configuration
– Pin multiplexing control
– Device boot configuration status
· ARM Interrupt and EDMA Event multiplexing control
· Special Peripheral Status and Control
– Timer64+ control
– USB PHY control
– VPSS clock and Video DAC control and status
– DDR I/O timing control and status
– DDR VTP control
– Clock out circuitry
– GIO de-bounce control
· Power Managment
– Deep Sleep Control
· Bandwidth Management
– Bus master DMA priority control
9.9.1 Bus Master DMA Priority Control
DM355 Master IDs
MSTID Master
0 ARM Instruction
1 ARM Data
2 Reserved
3 Reserved
4-7 Reserved
8 VPSS
9 MPEG/JPEG Coprocessor (MJCP)
10 EDMA
11-15 Reserved
16 EDMA Channel 0 read
17 EDMA Channel 0 write
18 EDMA Channel 1 read
19 EDMA Channel 1 write
20-31 Reserved
32 Reserved
33 Reserved
34 USB
35 Reserved
36 Reserved
37 Reserved
38-63 Reserved
9.10 System Control Register Descriptions
System Module (SYS) Registers
Offset Acronym Register Description Section
0h PINMUX0 PINMUX0 - Pin Mux 0 (Video In) Pin Mux Register Section 9.10.2
4h PINMUX1 PINMUX1 - Pin Mux 1 (Video Out) Pin Mux Register Section 9.10.3
8h PINMUX2 PINMUX2 - Pin Mux 2 (AEMIF) Pin Mux Register Section 9.10.4
Ch PINMUX3 PINMUX3 - Pin Mux 3 (GIO/Misc) Pin Mux Register Section 9.10.5
10h PINMUX4 PINMUX4 - Pin Mux 4 (Misc) Pin Mux Register Section 9.10.6
14h BOOTCFG Boot Configuration Section 9.10.7
18h ARM_INTMUX Multiplexing Control for Interrupts Section 9.10.8
1Ch EDMA_EVTMUX Multiplexing Control for EDMA Events Section 9.10.9
20h DDR_SLEW DDR Slew Rate Section 9.10.10
24h CLKOUT CLKOUT div/out Control Section 9.10.11
28h DEVICE_ID Device ID Section 9.10.12
2Ch VDAC_CONFIG Video DAC Configuration Section 9.10.13
30h TIMER64_CTL TIMER64_CTL - Timer64+ Input Control Section 9.10.14
34h USB_PHY_CTRL USB PHY Control Section 9.10.15
38h MISC Miscellaneous Control Section 9.10.16
3Ch MSTPRI0 Master Priorities Reg0 Section 9.10.17
40h MSTPRI1 Master Priorities Reg1 Section 9.10.18
44h VPSS_CLK_CTRL VPSS Clock Mux Control Section 9.10.19
48h DEEPSLEEP DEEPSLEEP Configuration Section 9.10.20
50h DEBOUNCE0 DEBOUNCE - Debounce for GIO0 Input Section 9.10.21
54h DEBOUNCE1 DEBOUNCE - Debounce for GIO1 Input Section 9.10.21
58h DEBOUNCE2 DEBOUNCE - Debounce for GIO2 Input Section 9.10.21
5Ch DEBOUNCE3 DEBOUNCE - Debounce for GIO3 Input Section 9.10.21
60h DEBOUNCE4 DEBOUNCE - Debounce for GIO4 Input Section 9.10.21
64h DEBOUNCE5 DEBOUNCE - Debounce for GIO5 Input Section 9.10.21
68h DEBOUNCE6 DEBOUNCE - Debounce for GIO6 Input Section 9.10.21
6Ch DEBOUNCE7 DEBOUNCE - Debounce for GIO7 Input Section 9.10.21
70h VTPIOCR VTP IO Control Register Section 9.10.22
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