2009年8月24日星期一
VPBE寄存器描述
1.PINMUX1
22 VCLK Enable VCLK
0 VCLK
1 GIO[68]
21-20 EXTCLK Enable EXTCLK (Video Out pin mux)
0 GIO[69]
1h EXTCLK
2h B2
3h PWM3
19-18 FIELD Enable FIELD (Video Out pin mux)
0 GIO[70]
1h FIELD
2h R2
3h PWM3
17 DCLD Enable DLCD signal output (Video Out pin mux)
0 LCD_OE or BRIGHT (set by LDCOUT.OES)
1 GIO[71]
16 HYSYNC Enable HVSYNC (Video Out pin mux)
0 HVSYNC and VSYNC
1 GIO[73:72]
15-14 COUT_0 Enable COUT[0] (Video Out pin mux)
0 GIO[74]
1h COUT[0]
2h PWM3
13-12 COUT_1 Enable COUT[1] (Video Out pin mux)
0\ GIO[75]
1h COUT[1]
2h PWM3
3h Reserved
11-10 COUT_2 Enable COUT[2] (Video Out pin mux)
0 GIO[76]
1h COUT[2]
2h PWM2
3h RTO3
9-8 COUT_3 Enable COUT[3] (Video Out pin mux)
0 GIO[77]
1h COUT[3]
2h PWM2
3h RTO2
7-6 COUT_4 Enable COUT[4] (Video Out pin mux)
0 GIO[78]
1h COUT[4]
2h PWM2
3h RTO1
5-4 COUT_5 Enable COUT[5] (Video Out pin mux)
0 GIO[79]
1h COUT[5]
2h PWM2
3h RTO0
3-2 COUT_6 Enable COUT[6] (Video Out pin mux)
0 GIO[80]
1h COUT[6]
2h PWM1
3h Reserved
1-0 COUT_7 Enable COUT[7] (Video Out pin mux)
0 GIO[81]
1h COUT[7]
2h PWM0
3h Reserved
3 VPBE Integration
VPBE实则是一个DMA主控器
VPBE不用时可让VPSSCLK.CLKCTRL.VPBE_CLK禁用，但若使用，则应先打开，再进行其它操作
3.1.1.4 VPSS Clock Mux Control Register (VPSS_CLK_CTRL)
6-5 VENC_CLK_SRC 27 MHz input source
0 PLL1 divided down
1 (EXTCRYSTAL2) External crystal 2
2h (EXTCRYSTAL1) External crystal 1
3h Reserved
4 DACCLKEN Video DAC clock enable
0 Disabled
1 Enabled
3 VENCLKEN VPBE/Video encoder clock enable
0 Disabled
1 Enabled
2 PCLK_INV Invert VPFE pixel clock (PCLK)
0 Disable VENC clock mux and CCDC receive normal PCLK
1 Enable VENC clock mux and CCDC receive inverted PCLK
1-0 VPSS_MUXSEL 0-3h VPSS clock selection
0 Use input set by VENC_CLK_SRC (typically 27 MHZ).
1h Reserved
2h EXTCLK mode. Use external VPBE clock input (DAC clock = EXTCLK).
3h PCLK mode. Use PCLK from VPFE (DAC clock = off).
3.1.1.5 MXI2 Oscillator Power Control：USB Physical Control Register (USB_PHY_CTRL)
11 DATAPOL USB PHY data polarity inversion
0 USB PHY data polarity, no inversion
1 USB PHY data polarity inversion
10 - 9 PHYCLKSRC USB PHY input clock source
0 24 MHz directly from crystal
1h 12 MHz (after dividing 36 MHz crystal by 3)
2h {PLLCTRL1.SYSCLK3) backup in case 27 MHz crystal is used.
3h Reserved
8 PHYCLKGD USB PHY power and clock good
0 BAD - PHY power not ramped or PLL not locked
1 GOOD - PHY power is good and PLL is locked
7 SESNDEN Session end comparator enable
0 DISABLE - Comparator disabled
1 ENABLE - Comparator enabled
6 VBDTCTEN VBUS comparator enabled
0 DISABLE - Comparators (except session end) disabled
1 ENABLE - Comparators (except session end) enabled
5 VBUSENS OTG analog block VBUSSENSE output status
0 ABSENT - VBUS not present (<0.5 V)
1 PRESENT - VBUS present (>0.5 V)
4 PHYPLLON USB PHY PLL suspend override
0 Normal PLL operation
1 Override PLL suspend state
3 Reserved Reserved
2 VPSS VPSS oscillator power down controlOSCPDWN
0 VPSS MXI2 powered on
1 VPSS MXI2 power off
1 OTGPDWN USB OTG analog block power down control
0 OTG analog block powered on
1 OTG analog block power off
0 PHYPDWN USB PHY power down control
0 PHY powered on
1 PHY power off
3.1.2 Resets
不要用SyncReset or SwRstDisable states of the PSC
3.3 Video DAC Configuration
在SYSTEM MODULE中VDAC_CONFIG 值，推荐：
· TRESB4R4 = 0x3
· TRESB4R2 = 0x8
· TRESB4R1 = 0x8
· TRIMBITS = 0x34
· PWD_BGZ = 1 (power-up VREF)
· SPEED = 1 (faster)
· PWD_VBUFZ = 1 (power-up video buffer)
· ACCUP_EN = 0 (default 1)
· DINV = 1 (invert)
3.3.1 Video DAC Configuration Register (VDAC CONFIG)
29-26 TRESB4R4 Resistance trimming control bit for VREF
25-22 TRESB4R2 Resistance trimming control bit for VREF
21-18 TRESB4R1 Resistance trimming control bit for VREF
17-11 TRIMBITS PNP transistor trimming control bit for VREF
10 PWD_BGZ Power Down of VREFF
0 power down
1 power Up
9 SPEED Faster operation of VREF transfer
0 Normal
1 Faster
8 TVINT TV cable connect status from DAC
0 Cable connected
1 Cable disconnected
7 PWD_VBUFZ Power down of video buffer
0 Power Down
1 Power UP
6-4 VREFSET VREF setting to vedio buffer
3 ACCUP_EN AC capacitor coupling externally to video buffer
0 Disable the coupling
1 Enable the coupling
2 DINV Data invert from VENC (inside the DAC)
0 No inversion - use only when VDAC is used without VREF and buffer
1 Inversion _ When VDAC is used with VREF and buffer
1 RESERVED Reserved
0 RESERVED Reserved
4.3 Master/Slave Mode Interface
Master Mode Configuration Registers
Acronym Register
HSPLS Horizontal sync pulse width
VSPLS Vertical sync pulse width
HINT Horizontal interval
HSTART Horizontal valid data start position
HVALID Horizontal data valid range
VINT Vertical interval
VSTART Vertical valid data start position
VVALID Vertical data valid range
HSDLY Horizontal sync delay
VSDLY Vertical sync delay
4.4.1 Video Window Constraints
1.用VIDEO WINDOW0作HD显示
2.当VIDEO WINDOW0作HD显示时，VIDEO WINDOW1禁用
4.4.2.1 DDR Addresses
OSD SDRAM Address Registers
SDRAM Address Register Window
VIDWIN0ADL Video window 0 address (low 16 bits)
VIDWIN1ADL Video window 1 address (low 16 bits)
VIDWINADH Video window addresses (upper bits)
OSDWIN0ADL OSD bitmap window 0 address (low 16 bits)
OSDWIN1ADL OSD bitmap window 1/attribute window address (low 16 bits)
OSDWINADH OSD bitmap window addresses (upper bits)
4.4.2.2 DDR Offsets
显示区域的每行尺寸偏移，可行显示一个影像的子集（部分）
OSD SDRAM Offset Registers
SDRAM Address Register Window
VIDWIN0OFST Video Window 0 SDRAM offset register
VIDWIN1OFST Video Window 1 SDRAM offset register
OSDWIN0OFST OSD Bitmap Window 0 SDRAM offset register
OSDWIN1OFST OSD Bitmap Window 1/Attribute Window SDRAM offset register
4.4.2.3 Window Positioning
1. BASEP_X and BASEP_Y 以HD，VD前沿为参考点
2. 当VENC为INTERFACE （交错模式），则YP，YL的定义为每FIELD的行数；若为PROGRESSIVE则定义为第FRAME的行数。
OSD Window Positioning Registers
Window Positioning Registers Window
VIDWIN0XP Video Window 0 start position and size registers
VIDWIN0YP
VIDWIN0XL 行像素
VIDWIN0YL 行数
====================================================================================
VIDWIN1XP Video Window 1 start position and size registers
VIDWIN1YP
VIDWIN1XL
VIDWIN1YL
======================================================================================
OSDWIN0XP OSD Bitmap Window 0 start position and size registers
OSDWIN0YP
OSDWIN0XL
OSDWIN0YL
OSDWIN1XP OSD Bitmap Window 1/Attribute Window start position and size registers
OSDWIN1YP
OSDWIN1XL
OSDWIN1YL
======================================================================================
CURXP Hardware cursor start position and size registers
CURYP
CURXL
CURYL
4.4.2.4 Window Mode – Field/Frame
OSD Field/Frame Mode Registers
Register.Field Description
VIDWINMD.VFF0 Video Window 0 Field/Frame specification
VIDWINMD.VFF1 Video Window 1 Field/Frame specification
OSDWIN0MD.OFF0 OSD Bitmap Window 0 Field/Frame specification
OSDWIN1MD.OFF1 OSD Bitmap Window 1 Field/Frame specification
OSDATRMD.OFFA OSD Attribute Window Field/Frame specification
(same address/offset as for OSD Bitmap Window 1)
4.4.2.4.1 Frame Mode
此时在DDR中的数据是以PROGRESSIVE模式存放。
此时VENC只能为INTERLACE，WINDOW HEIGHT=LINES/FIELD=1/2 DISPLAY HEIGHT，以2 X OFFSET 增加地址
4.4.2.4.2 Field Mode
1.VENC为INTERLACE模式，WINDOW HEIGHT=LINES/FIELD=1/2 DISPLAY HEIGHT，后FIELD重读DDR中前FIELD处地址空间数据
2.VENC为PROGRESSIVE模式，WINDOW HEIGHT=LINES/FRAME=FULL DISPLAY HEIGHT
4.4.2.5 Window Scaling
有两种方式放大：
一种是以像素COPY方，x2 and x4
另一种是以线性插值方式，x9/8 （640转720）and x3/2 （640转960）in horizontal direction and x6/5 （480转576）in vertical direction.
4.4.2.5.1 Window Zooming
在DDR中选取要放大的数据区域，在设置屏幕显示位置
OSD Window Zoom Registers
Register. Field Description
VIDWINMD.VHZ0 Video Window 0 Horizontal Zoom
VIDWINMD.VVZ0 Video Window 0 Vertical Zoom
VIDWINMD.VHZ1 Video Window 1 Horizontal Zoom
VIDWINMD.VVZ1 Video Window 1 Vertical Zoom
OSDWIN0MD.OHZ0 Bitmap Window 0 Horizontal Zoom
OSDWIN0MD.OVZ0 Bitmap Window 0 Vertical Zoom
OSDWIN1MD.OHZ1 Bitmap Window 1 Horizontal Zoom
OSDWIN1MD.OVZ1 Bitmap Window 1 Vertical Zoom
4.4.2.5.2 Window Scaling – Square Pixels for NTSC/PAL Analog Output or Display Matching
Normal OSD Window Expansion Registers
Register Field Description
MODE.VHRSZ Video Window Horizontal 9/8 Expansion
MODE.VVRSZ Video Window Vertical 6/5 Expansion
MODE.V0EFC Video Window 0 smoothing filter enable (with MODE.EF)
MODE.V1EFC Video Window 1 smoothing filter enable (with MODE.EF)
MODE.EF Video Window smoothing filter (maximum line width is 720)
MODE.OHRSZ Video Window Horizontal 9/8 Expansion
MODE.OVRSZ Video Window Vertical 6/5 Expansion
Extended OSD Window Expansion Registers
Register.Field Description
EXTMODE.EXPMDSEL Sets filtering mode before expansion
EXTMODE.SCRNHEXP Global H expansion on all windows
EXTMODE.SCRNVEXP Global V expansion for all windows
EXTMODE.OSDHRSZ15 Bitmap window 1.5x expansion if normal filtering done
EXTMODE.VIDHRAZ15 Video window 1.5x expansion if normal filtering done
4.4.2.5.3 Zoom and Expansion Filter Usage
vertical expansion filter 优先权比 vertical zoom filter高
4.4.2.5.4 Window Positioning Limits for When Using Horizontal Expansion
当水平Expansion时，同类型窗口有位置限制，不能随便设置
4.4.2.5.6 Vertical Boundary Processing
4.4.2.6 OSD Background Color
OSD Background Color Registers
Register. Field Description
MODE.BCLUT Selects the color lookup table to be used (ROM or RAM). Note that there
are two ROM tables and the selection for the other windows also applies
here (MISCCTL.RSEL).
MODE.CABG Background color. 8-bit offset into color lookup table.
Pixel Arrangement in the Display（SDRAM）
Left, Top
P0 P1 P2 P3 P4 P5 P6 P7 ...
4.4.3.2 Expansion and Anti-Flicker Filter for Video Window
Expansion and Anti-Flicker Filter for Video Window
Register.Field Description
MODE.EF Expansion filter enable. Only use when EXTMODE.EXPMDSEL = 0
WIDWINMD.VFINV Inverts application of the two sets of expansion filter
coefficients betweenfield 0 and field 1.
WIDWINMD.VnEFC Enables different anti-flicker coefficients for each field
EXTMODE.EXPMDSEL Extended mode expansion filtering mode select
EXTMODE.ZMFILVnVEN Extended mode - video window n vertical zoom filter type (x6/5)
EXTMODE.ZMFILVnHEN Extended mode - video window n horizontal zoom filter type
EXTMODE.EXPFILHEN Extended mode - video window horizontal expansion filter enable (x9/8, x1/5)
EXTMODE.EXPFILVEN Extended mode - video window vertical expansion filter enable (x6/5)
4.4.3.2.2 Video Window Filtering - Vertical Direction
4.4.3.2.2.1 Vertical x1 Anti-Flicker (Expansion) Filter (Field Rate Conversion)
（FIELD-BASED IMAGE TO DISPLAY）
Vertical x1 Anti-Flicker Filter Control Registers
Register Field Value
WIDWINMD.FSINV 1
or
WIDWINMD.VFINV
=============================================================================================
WIDWINMD.VnEFC 0 or 1
Operation of Vertical x1 Anti-Flicker Filter Control Registers
Invert bit (VIDWINMD.VFINF or MODE.FSINV) 0 1
Expand Filter (V)
Coefficient bit (VIDWINMD.VnEFC) Different (due to same field source)
ON FID = 0 1 FID = 0 2
FID = 1 2 FID = 1 1
OFF FID = 0 1 FID = 0 1
FID = 1 1 FID = 1 1
4.4.3.2.2.2 Vertical x1 Anti-Flicker (Expansion) Filter (Without Field Rate Conversion):the filtering function is not applied(不用FILER）
FIELD-BASED IMAGE TO DISPLAY
Operation of Vertical x1 Anti-Flicker Filter Control Registers
Invert bit (VIDWINMD.VFINF or MODE.FSINV) 0 1
Expand Filter (V)
Coefficient Bit (VIDWINMD.VnEFC) Same (due to different field source)
ON FID = 0 1 FID = 0 1
FID = 1 1 FID = 1 1
OFF FID = 0 1 FID = 0 1
FID = 1 1 FID = 1 1
4.4.3.2.2.3 Vertical x1 Anti-Flicker (Expansion) Filter (Frame Source Data Case)
FRAME-BASED IMAGE
the filtering function is not applied（FILER功能不用）
Operation of Vertical x1 Anti-Flicker Filter for Frame Mode
Invert bit (VIDWINMD.VFINF or MODE.FSINV) 0 1 Expand Filter (V)
Coefficient bit (VIDWINMD.VnEFC) Different (due to same field source)
ON FID = 0 1 FID = 0 2
FID = 1 2 FID = 1 1
OFF FID = 0 1 FID = 0 2
FID = 1 2 FID = 1 1
4.4.4 Bitmap Windows
4.4.4.1 Color LookUp Tables
有三个LUT，两个ROM的，一个RAM的，RAM可编程，编程顺序如下：
1. 等 MISCCTL.CPBSY 清 0.
2. 写Y 及 Cb 到 CLUTRAMYCB .
3. 写Cr 及 CLUT address 到 CLUTRAMCR register. The address 为CLUT RAM中Y,CB,CR的偏移值
4. 重复以上.
OSD Color Look-Up Table Registers
Register.Field Description
ROM color look-up table MISCCTL.RSEL Selects the ROM color look-p table to use for
all options that selection select the
ROM table (0=DM270, 1=DM320)
Background color selection MODE.BCLUT Background CLUT selection (ROM or RAM)
MODE.CABG Background CLUT selection (offset into 256- bit table)
Cursor CLUT selection RECTCUR.CLUTSR Cursor CLUT selection (ROM or RAM)
RECTCUR.RCAD Rectangular Cursor color address within
CLUT(offset into256-bit table)
Bitmap window CLUT OSDWIN0MD.CLUTS0 Window 0 CLUT selection (ROM or RAM)
selections OSDWIN1MD.CLUTS1 Window 1 CLUT selection (ROM or RAM)
RAM CLUT Setup/Write CLUTRAMYCB.Y CLUTRAM Y (luma) value
CLUTRAMYCB.CB CLUTRAM CB (chroma) value
CLUTRAMCR.CR CLUTRAM CR (chroma) value
CLUTRAMCR.CADDR CLUTRAM address offset (writes all values)
MISCCTL.CPBUSY Indicates if busy when writing to CLUT RAM
CLUT Mapping for 1-Bit, 2-Bit, or 4-Bit Bitmaps
Register.Field Color Corresponding to Bitmap Value
(n = 0 or 1 for OSD Bitmap
Window 0 or 1, respectively) 4-Bit Bitmap 2-Bit Bitmap 1-Bit Bitmap
WnBMP01.PAL00 0 0 0
WnBMP01.PAL01 1 - -
WnBMP23.PAL02 2 - -
WnBMP23.PAL03 3 - -
WnBMP45.PAL04 4 - -
WnBMP45.PAL05 5 1 -
WnBMP67.PAL06 6 - -
WnBMP67.PAL07 7 - -
WnBMP89.PAL08 8 - -
WnBMP89.PAL09 9 - -
WnBMPAB.PAL10 10 2 -
WnBMPAB.PAL11 11 - -
WnBMPCD.PAL12 12 - -
WnBMPCD.PAL13 13 - -
WnBMPEF.PAL14 14 - -
WnBMPEF.PAL15 15 3 1
22 VCLK Enable VCLK
0 VCLK
1 GIO[68]
21-20 EXTCLK Enable EXTCLK (Video Out pin mux)
0 GIO[69]
1h EXTCLK
2h B2
3h PWM3
19-18 FIELD Enable FIELD (Video Out pin mux)
0 GIO[70]
1h FIELD
2h R2
3h PWM3
17 DCLD Enable DLCD signal output (Video Out pin mux)
0 LCD_OE or BRIGHT (set by LDCOUT.OES)
1 GIO[71]
16 HYSYNC Enable HVSYNC (Video Out pin mux)
0 HVSYNC and VSYNC
1 GIO[73:72]
15-14 COUT_0 Enable COUT[0] (Video Out pin mux)
0 GIO[74]
1h COUT[0]
2h PWM3
13-12 COUT_1 Enable COUT[1] (Video Out pin mux)
0\ GIO[75]
1h COUT[1]
2h PWM3
3h Reserved
11-10 COUT_2 Enable COUT[2] (Video Out pin mux)
0 GIO[76]
1h COUT[2]
2h PWM2
3h RTO3
9-8 COUT_3 Enable COUT[3] (Video Out pin mux)
0 GIO[77]
1h COUT[3]
2h PWM2
3h RTO2
7-6 COUT_4 Enable COUT[4] (Video Out pin mux)
0 GIO[78]
1h COUT[4]
2h PWM2
3h RTO1
5-4 COUT_5 Enable COUT[5] (Video Out pin mux)
0 GIO[79]
1h COUT[5]
2h PWM2
3h RTO0
3-2 COUT_6 Enable COUT[6] (Video Out pin mux)
0 GIO[80]
1h COUT[6]
2h PWM1
3h Reserved
1-0 COUT_7 Enable COUT[7] (Video Out pin mux)
0 GIO[81]
1h COUT[7]
2h PWM0
3h Reserved
3 VPBE Integration
VPBE实则是一个DMA主控器
VPBE不用时可让VPSSCLK.CLKCTRL.VPBE_CLK禁用，但若使用，则应先打开，再进行其它操作
3.1.1.4 VPSS Clock Mux Control Register (VPSS_CLK_CTRL)
6-5 VENC_CLK_SRC 27 MHz input source
0 PLL1 divided down
1 (EXTCRYSTAL2) External crystal 2
2h (EXTCRYSTAL1) External crystal 1
3h Reserved
4 DACCLKEN Video DAC clock enable
0 Disabled
1 Enabled
3 VENCLKEN VPBE/Video encoder clock enable
0 Disabled
1 Enabled
2 PCLK_INV Invert VPFE pixel clock (PCLK)
0 Disable VENC clock mux and CCDC receive normal PCLK
1 Enable VENC clock mux and CCDC receive inverted PCLK
1-0 VPSS_MUXSEL 0-3h VPSS clock selection
0 Use input set by VENC_CLK_SRC (typically 27 MHZ).
1h Reserved
2h EXTCLK mode. Use external VPBE clock input (DAC clock = EXTCLK).
3h PCLK mode. Use PCLK from VPFE (DAC clock = off).
3.1.1.5 MXI2 Oscillator Power Control：USB Physical Control Register (USB_PHY_CTRL)
11 DATAPOL USB PHY data polarity inversion
0 USB PHY data polarity, no inversion
1 USB PHY data polarity inversion
10 - 9 PHYCLKSRC USB PHY input clock source
0 24 MHz directly from crystal
1h 12 MHz (after dividing 36 MHz crystal by 3)
2h {PLLCTRL1.SYSCLK3) backup in case 27 MHz crystal is used.
3h Reserved
8 PHYCLKGD USB PHY power and clock good
0 BAD - PHY power not ramped or PLL not locked
1 GOOD - PHY power is good and PLL is locked
7 SESNDEN Session end comparator enable
0 DISABLE - Comparator disabled
1 ENABLE - Comparator enabled
6 VBDTCTEN VBUS comparator enabled
0 DISABLE - Comparators (except session end) disabled
1 ENABLE - Comparators (except session end) enabled
5 VBUSENS OTG analog block VBUSSENSE output status
0 ABSENT - VBUS not present (<0.5 V)
1 PRESENT - VBUS present (>0.5 V)
4 PHYPLLON USB PHY PLL suspend override
0 Normal PLL operation
1 Override PLL suspend state
3 Reserved Reserved
2 VPSS VPSS oscillator power down controlOSCPDWN
0 VPSS MXI2 powered on
1 VPSS MXI2 power off
1 OTGPDWN USB OTG analog block power down control
0 OTG analog block powered on
1 OTG analog block power off
0 PHYPDWN USB PHY power down control
0 PHY powered on
1 PHY power off
3.1.2 Resets
不要用SyncReset or SwRstDisable states of the PSC
3.3 Video DAC Configuration
在SYSTEM MODULE中VDAC_CONFIG 值，推荐：
· TRESB4R4 = 0x3
· TRESB4R2 = 0x8
· TRESB4R1 = 0x8
· TRIMBITS = 0x34
· PWD_BGZ = 1 (power-up VREF)
· SPEED = 1 (faster)
· PWD_VBUFZ = 1 (power-up video buffer)
· ACCUP_EN = 0 (default 1)
· DINV = 1 (invert)
3.3.1 Video DAC Configuration Register (VDAC CONFIG)
29-26 TRESB4R4 Resistance trimming control bit for VREF
25-22 TRESB4R2 Resistance trimming control bit for VREF
21-18 TRESB4R1 Resistance trimming control bit for VREF
17-11 TRIMBITS PNP transistor trimming control bit for VREF
10 PWD_BGZ Power Down of VREFF
0 power down
1 power Up
9 SPEED Faster operation of VREF transfer
0 Normal
1 Faster
8 TVINT TV cable connect status from DAC
0 Cable connected
1 Cable disconnected
7 PWD_VBUFZ Power down of video buffer
0 Power Down
1 Power UP
6-4 VREFSET VREF setting to vedio buffer
3 ACCUP_EN AC capacitor coupling externally to video buffer
0 Disable the coupling
1 Enable the coupling
2 DINV Data invert from VENC (inside the DAC)
0 No inversion - use only when VDAC is used without VREF and buffer
1 Inversion _ When VDAC is used with VREF and buffer
1 RESERVED Reserved
0 RESERVED Reserved
4.3 Master/Slave Mode Interface
Master Mode Configuration Registers
Acronym Register
HSPLS Horizontal sync pulse width
VSPLS Vertical sync pulse width
HINT Horizontal interval
HSTART Horizontal valid data start position
HVALID Horizontal data valid range
VINT Vertical interval
VSTART Vertical valid data start position
VVALID Vertical data valid range
HSDLY Horizontal sync delay
VSDLY Vertical sync delay
4.4.1 Video Window Constraints
1.用VIDEO WINDOW0作HD显示
2.当VIDEO WINDOW0作HD显示时，VIDEO WINDOW1禁用
4.4.2.1 DDR Addresses
OSD SDRAM Address Registers
SDRAM Address Register Window
VIDWIN0ADL Video window 0 address (low 16 bits)
VIDWIN1ADL Video window 1 address (low 16 bits)
VIDWINADH Video window addresses (upper bits)
OSDWIN0ADL OSD bitmap window 0 address (low 16 bits)
OSDWIN1ADL OSD bitmap window 1/attribute window address (low 16 bits)
OSDWINADH OSD bitmap window addresses (upper bits)
4.4.2.2 DDR Offsets
显示区域的每行尺寸偏移，可行显示一个影像的子集（部分）
OSD SDRAM Offset Registers
SDRAM Address Register Window
VIDWIN0OFST Video Window 0 SDRAM offset register
VIDWIN1OFST Video Window 1 SDRAM offset register
OSDWIN0OFST OSD Bitmap Window 0 SDRAM offset register
OSDWIN1OFST OSD Bitmap Window 1/Attribute Window SDRAM offset register
4.4.2.3 Window Positioning
1. BASEP_X and BASEP_Y 以HD，VD前沿为参考点
2. 当VENC为INTERFACE （交错模式），则YP，YL的定义为每FIELD的行数；若为PROGRESSIVE则定义为第FRAME的行数。
OSD Window Positioning Registers
Window Positioning Registers Window
VIDWIN0XP Video Window 0 start position and size registers
VIDWIN0YP
VIDWIN0XL 行像素
VIDWIN0YL 行数
====================================================================================
VIDWIN1XP Video Window 1 start position and size registers
VIDWIN1YP
VIDWIN1XL
VIDWIN1YL
======================================================================================
OSDWIN0XP OSD Bitmap Window 0 start position and size registers
OSDWIN0YP
OSDWIN0XL
OSDWIN0YL
OSDWIN1XP OSD Bitmap Window 1/Attribute Window start position and size registers
OSDWIN1YP
OSDWIN1XL
OSDWIN1YL
======================================================================================
CURXP Hardware cursor start position and size registers
CURYP
CURXL
CURYL
4.4.2.4 Window Mode – Field/Frame
OSD Field/Frame Mode Registers
Register.Field Description
VIDWINMD.VFF0 Video Window 0 Field/Frame specification
VIDWINMD.VFF1 Video Window 1 Field/Frame specification
OSDWIN0MD.OFF0 OSD Bitmap Window 0 Field/Frame specification
OSDWIN1MD.OFF1 OSD Bitmap Window 1 Field/Frame specification
OSDATRMD.OFFA OSD Attribute Window Field/Frame specification
(same address/offset as for OSD Bitmap Window 1)
4.4.2.4.1 Frame Mode
此时在DDR中的数据是以PROGRESSIVE模式存放。
此时VENC只能为INTERLACE，WINDOW HEIGHT=LINES/FIELD=1/2 DISPLAY HEIGHT，以2 X OFFSET 增加地址
4.4.2.4.2 Field Mode
1.VENC为INTERLACE模式，WINDOW HEIGHT=LINES/FIELD=1/2 DISPLAY HEIGHT，后FIELD重读DDR中前FIELD处地址空间数据
2.VENC为PROGRESSIVE模式，WINDOW HEIGHT=LINES/FRAME=FULL DISPLAY HEIGHT
4.4.2.5 Window Scaling
有两种方式放大：
一种是以像素COPY方，x2 and x4
另一种是以线性插值方式，x9/8 （640转720）and x3/2 （640转960）in horizontal direction and x6/5 （480转576）in vertical direction.
4.4.2.5.1 Window Zooming
在DDR中选取要放大的数据区域，在设置屏幕显示位置
OSD Window Zoom Registers
Register. Field Description
VIDWINMD.VHZ0 Video Window 0 Horizontal Zoom
VIDWINMD.VVZ0 Video Window 0 Vertical Zoom
VIDWINMD.VHZ1 Video Window 1 Horizontal Zoom
VIDWINMD.VVZ1 Video Window 1 Vertical Zoom
OSDWIN0MD.OHZ0 Bitmap Window 0 Horizontal Zoom
OSDWIN0MD.OVZ0 Bitmap Window 0 Vertical Zoom
OSDWIN1MD.OHZ1 Bitmap Window 1 Horizontal Zoom
OSDWIN1MD.OVZ1 Bitmap Window 1 Vertical Zoom
4.4.2.5.2 Window Scaling – Square Pixels for NTSC/PAL Analog Output or Display Matching
Normal OSD Window Expansion Registers
Register Field Description
MODE.VHRSZ Video Window Horizontal 9/8 Expansion
MODE.VVRSZ Video Window Vertical 6/5 Expansion
MODE.V0EFC Video Window 0 smoothing filter enable (with MODE.EF)
MODE.V1EFC Video Window 1 smoothing filter enable (with MODE.EF)
MODE.EF Video Window smoothing filter (maximum line width is 720)
MODE.OHRSZ Video Window Horizontal 9/8 Expansion
MODE.OVRSZ Video Window Vertical 6/5 Expansion
Extended OSD Window Expansion Registers
Register.Field Description
EXTMODE.EXPMDSEL Sets filtering mode before expansion
EXTMODE.SCRNHEXP Global H expansion on all windows
EXTMODE.SCRNVEXP Global V expansion for all windows
EXTMODE.OSDHRSZ15 Bitmap window 1.5x expansion if normal filtering done
EXTMODE.VIDHRAZ15 Video window 1.5x expansion if normal filtering done
4.4.2.5.3 Zoom and Expansion Filter Usage
vertical expansion filter 优先权比 vertical zoom filter高
4.4.2.5.4 Window Positioning Limits for When Using Horizontal Expansion
当水平Expansion时，同类型窗口有位置限制，不能随便设置
4.4.2.5.6 Vertical Boundary Processing
4.4.2.6 OSD Background Color
OSD Background Color Registers
Register. Field Description
MODE.BCLUT Selects the color lookup table to be used (ROM or RAM). Note that there
are two ROM tables and the selection for the other windows also applies
here (MISCCTL.RSEL).
MODE.CABG Background color. 8-bit offset into color lookup table.
Pixel Arrangement in the Display（SDRAM）
Left, Top
P0 P1 P2 P3 P4 P5 P6 P7 ...
4.4.3.2 Expansion and Anti-Flicker Filter for Video Window
Expansion and Anti-Flicker Filter for Video Window
Register.Field Description
MODE.EF Expansion filter enable. Only use when EXTMODE.EXPMDSEL = 0
WIDWINMD.VFINV Inverts application of the two sets of expansion filter
coefficients betweenfield 0 and field 1.
WIDWINMD.VnEFC Enables different anti-flicker coefficients for each field
EXTMODE.EXPMDSEL Extended mode expansion filtering mode select
EXTMODE.ZMFILVnVEN Extended mode - video window n vertical zoom filter type (x6/5)
EXTMODE.ZMFILVnHEN Extended mode - video window n horizontal zoom filter type
EXTMODE.EXPFILHEN Extended mode - video window horizontal expansion filter enable (x9/8, x1/5)
EXTMODE.EXPFILVEN Extended mode - video window vertical expansion filter enable (x6/5)
4.4.3.2.2 Video Window Filtering - Vertical Direction
4.4.3.2.2.1 Vertical x1 Anti-Flicker (Expansion) Filter (Field Rate Conversion)
（FIELD-BASED IMAGE TO DISPLAY）
Vertical x1 Anti-Flicker Filter Control Registers
Register Field Value
WIDWINMD.FSINV 1
or
WIDWINMD.VFINV
=============================================================================================
WIDWINMD.VnEFC 0 or 1
Operation of Vertical x1 Anti-Flicker Filter Control Registers
Invert bit (VIDWINMD.VFINF or MODE.FSINV) 0 1
Expand Filter (V)
Coefficient bit (VIDWINMD.VnEFC) Different (due to same field source)
ON FID = 0 1 FID = 0 2
FID = 1 2 FID = 1 1
OFF FID = 0 1 FID = 0 1
FID = 1 1 FID = 1 1
4.4.3.2.2.2 Vertical x1 Anti-Flicker (Expansion) Filter (Without Field Rate Conversion):the filtering function is not applied(不用FILER）
FIELD-BASED IMAGE TO DISPLAY
Operation of Vertical x1 Anti-Flicker Filter Control Registers
Invert bit (VIDWINMD.VFINF or MODE.FSINV) 0 1
Expand Filter (V)
Coefficient Bit (VIDWINMD.VnEFC) Same (due to different field source)
ON FID = 0 1 FID = 0 1
FID = 1 1 FID = 1 1
OFF FID = 0 1 FID = 0 1
FID = 1 1 FID = 1 1
4.4.3.2.2.3 Vertical x1 Anti-Flicker (Expansion) Filter (Frame Source Data Case)
FRAME-BASED IMAGE
the filtering function is not applied（FILER功能不用）
Operation of Vertical x1 Anti-Flicker Filter for Frame Mode
Invert bit (VIDWINMD.VFINF or MODE.FSINV) 0 1 Expand Filter (V)
Coefficient bit (VIDWINMD.VnEFC) Different (due to same field source)
ON FID = 0 1 FID = 0 2
FID = 1 2 FID = 1 1
OFF FID = 0 1 FID = 0 2
FID = 1 2 FID = 1 1
4.4.4 Bitmap Windows
4.4.4.1 Color LookUp Tables
有三个LUT，两个ROM的，一个RAM的，RAM可编程，编程顺序如下：
1. 等 MISCCTL.CPBSY 清 0.
2. 写Y 及 Cb 到 CLUTRAMYCB .
3. 写Cr 及 CLUT address 到 CLUTRAMCR register. The address 为CLUT RAM中Y,CB,CR的偏移值
4. 重复以上.
OSD Color Look-Up Table Registers
Register.Field Description
ROM color look-up table MISCCTL.RSEL Selects the ROM color look-p table to use for
all options that selection select the
ROM table (0=DM270, 1=DM320)
Background color selection MODE.BCLUT Background CLUT selection (ROM or RAM)
MODE.CABG Background CLUT selection (offset into 256- bit table)
Cursor CLUT selection RECTCUR.CLUTSR Cursor CLUT selection (ROM or RAM)
RECTCUR.RCAD Rectangular Cursor color address within
CLUT(offset into256-bit table)
Bitmap window CLUT OSDWIN0MD.CLUTS0 Window 0 CLUT selection (ROM or RAM)
selections OSDWIN1MD.CLUTS1 Window 1 CLUT selection (ROM or RAM)
RAM CLUT Setup/Write CLUTRAMYCB.Y CLUTRAM Y (luma) value
CLUTRAMYCB.CB CLUTRAM CB (chroma) value
CLUTRAMCR.CR CLUTRAM CR (chroma) value
CLUTRAMCR.CADDR CLUTRAM address offset (writes all values)
MISCCTL.CPBUSY Indicates if busy when writing to CLUT RAM
CLUT Mapping for 1-Bit, 2-Bit, or 4-Bit Bitmaps
Register.Field Color Corresponding to Bitmap Value
(n = 0 or 1 for OSD Bitmap
Window 0 or 1, respectively) 4-Bit Bitmap 2-Bit Bitmap 1-Bit Bitmap
WnBMP01.PAL00 0 0 0
WnBMP01.PAL01 1 - -
WnBMP23.PAL02 2 - -
WnBMP23.PAL03 3 - -
WnBMP45.PAL04 4 - -
WnBMP45.PAL05 5 1 -
WnBMP67.PAL06 6 - -
WnBMP67.PAL07 7 - -
WnBMP89.PAL08 8 - -
WnBMP89.PAL09 9 - -
WnBMPAB.PAL10 10 2 -
WnBMPAB.PAL11 11 - -
WnBMPCD.PAL12 12 - -
WnBMPCD.PAL13 13 - -
WnBMPEF.PAL14 14 - -
WnBMPEF.PAL15 15 3 1
4.4.4.3 Bitmap Window Blending and Transparency
Bitmap Transparency and Blending Settings
Transparency Blending Factor
OSDWINnMD.TEn OSDWINnMD.BLNDn OSD Window Contribution Video Contribution
OFF 0 0 1
1 1/8 7/8
2 2/8 6/8
3 3/8 5/8
4 4/8 4/8
5 5/8 3/8
6 6/8 2/8
7 1 0
ON If pixel value is equal to 0:
0 0 1
1 1/8 7/8
2 2/8 6/8
3 3/8 5/8
4 4/8 4/8
5 5/8 3/8
6 6/8 2/8
7 1 0
If pixel value is not equal to 0:
X 1 0
Bitmap Transparency and Blending Settings
Transparency Blending Factor
OSDWINnMD.TEn OSDWINnMD.BLNDn OSD Window Contribution Video Contribution
OFF 0 0 1
1 1/8 7/8
2 2/8 6/8
3 3/8 5/8
4 4/8 4/8
5 5/8 3/8
6 6/8 2/8
7 1 0
ON If pixel value is equal to 0:
0 0 1
1 1/8 7/8
2 2/8 6/8
3 3/8 5/8
4 4/8 4/8
5 5/8 3/8
6 6/8 2/8
7 1 0
If pixel value is not equal to 0:
X 1 0
华盛顿邮报诗歌比赛
华盛顿邮报搞了一个比赛，要求写两行押韵的诗，第一行能多浪漫就多浪漫，第二行能多不浪漫就多不浪漫，以下是一些入选作品
==========================================
My darling, my lover, my beautiful wife:
Marrying you has screwed up my life
我的心肝，我的挚爱，我美丽的贤妻，
我这辈子就毁在你手里。
==========================================
My darling, my lover, my beautiful wife:
Marrying you has screwed up my life
我的心肝，我的挚爱，我美丽的贤妻，
我这辈子就毁在你手里。
I see your face when I am dreaming.
That's why I always wake up screaming.
你的容颜依稀入梦境，
于是我在尖叫中惊醒。
Kind, intelligent, loving and hot;
This describes everything you are not.
善良、聪慧、多情而性感，
可惜这些你一条都不占。
Love may be beautiful, love may be bliss,
But I only slept with you 'cause I was pissed.
爱是上天赐福，爱情多么美好，
可我与你同眠只是因为喝高。
I thought that I could love no other
-- that is until I met your brother.
曾以为一生只爱你一个
直到遇见你的二表哥。
Roses are red, violets are blue, sugar is sweet, and so are you.
But the roses are wilting, the violets are dead,the sugar bowl's empty and
so is your head.
娇艳的紫罗兰，鲜红的玫瑰，甜蜜的糖，就像你一样美。
但紫罗兰会凋谢，玫瑰会枯黄，糖碗空空如也，和你的脑袋一样。
I want to feel your sweet embrace;
But don't take that paper bag off your face.
我渴望你温柔的拥抱，
但别把你脸上的面具摘掉。
I love your smile, your face, and your eyes
Damn, I'm good at telling lies!
我爱你的明眸，你的脸庞，你的微笑，
妈的，我真是说谎不打草稿！
My love, you take my breath away.
What have you stepped in to smell this way?
爱人啊，你简直让我窒息，
你在哪沾上的一身臭气？
My feelings for you no words can tell,
Except for maybe "Go to hell."
我对你的深情无法付诸言语，
除了一句"滚一边去"！
What inspired this amorous rhyme?
Two parts vodka, one part lime.
是什么激发了我多情的诗篇？
伏特加两杯，酸柠檬一片。
VPFE寄存器描述
寄存器描述:
一.CCDC
1.Synchronization Enable Register (SYNCEN)
0:VDHDEN
1:WEN
2.MODESET
15:FLDSTAT 0:ODD FIELD 1:EVEN FIELD
14:LPF 3-tap Low-Pass (anti-aliasing) filter for ccd data 0:off 1:on
13-12:INPMOD INPUT MODE 0:CCD RAW DATA 1:YCBCR 16BIT 2:YCBCR 8BIT
11:PACK8 0:NORMAL 16BIT TO SDRAM 1:PACK8 BIT TO SDRAM
10-8:DATASFT 0:NO SHIFT 1-6:SHIFT 1-6BIT
7:FLDMODE 0:NON-INTERFACED 1：INTERFACED （若EXWEN =1，则需为0）
6:DATAPOL 0:NORMAL 1:ONE'S CONPLEMENT
5:EXWEN 0:不用外部WEN 1:用外部VD/HD作为写SDRAM的信号
4:FLDPOL 0:POSITIVE 1:NEGATIVE
3:HDPOL 意思同上
2:VDPOL 意思同上
0:VDHDOUT 0:VD,HD INPUT 1:VD,HD OUTPUT
3. Horizontal Size Register (HSIZE)
12:ADR_UPDT SDRAM 地址更新方式0:自动增加 1:自动减少
11-0:LNOFST SDRAM中行尺寸,32BYTE为单位即16或32PIXELS
4.SDRAM Line Offset Register (SDOFST)
14：FIINV 0：NON INVERSE 1：INVERSE
13-12：FOFST Line offset value of odd field (FID = 1) 0-3：+1 - +4
11-9：LOFST0 Line offset values of even line and even field (FID = 0) 0-7：+1 - -4
8-6：LOFST1 Line offset values of odd line and even field (FID = 0) 同上
5-3：LOFST2 Line offset values of even line and odd field (FID = 1) 同上
2-0：LOFST3 Line offset values of odd line and odd field (FID = 1)同上
5.SDRAM Address - High Register (STADRH)
6.SDRAM Address - LOW Register (STADRL)
7.CCD Color Pattern Register (COLPTN)
8. CCD Gain Adjustment - R/Ye Register (RYEGAIN)
CCD Gain Adjustment - Gr/Cy Register (GRCYGAIN)
CCD Gain Adjustment - Gb/G Register (GBGGAIN)
CCD Gain Adjustment - B/Mg Register (BMGGAIN)
CCD Offset Adjustment Register (OFFSET)
9.Output Clipping Value Register (OUTCLIP)
10.VD Interrupt #0 Register (VDINT0) 中断设定行数
11. VD Interrupt #1 Register (VDINT1)
12. Gamma Correction Settings Register (GAMMAWD)
11-10:MFIL1 Median filter mode for IPIPE 0:no filer 1:average filer 2:median filer
9-8: MFIL1 Median Filter for SDRAM capture.值同上
5：CFAP CFA Pattern. 0：Mosaic 1：Stripe
4-2：GWDI Gamma Width Input (For A-LAW table & H3A port)
0：BITS 13-4 1：12-3 2：11-2 3：10-1 4：9-0
0：CCDTBL Apply Gamma (A-LAW) to CCDC data saved to SDRAM 0：DISABLE 1：ENABLE
13. REC656 Control Register (REC656IF)
1: ECCFVH FVH error correction enable 0:DISABLE 1:ENABLE
0: R656ON REC656 interface enable 0:DISABLE 1:ENABLE
14. CCD Configuration Register (CCDCFG)
15:VDLC Enable synchronizing function regs on VSYNC. 0:Latched on VSYNC. 1:NO LATCHED
13:MSBINVI MSB of Chroma input signal stored to SDRAM inverted.0:NORMAL 1:MSB INVERTED
12:BSWD Byte swap data stored to SDRAM. 0:NORMAL 1:BYTE SWAP
11:Y8POS Location of Y signal when YCbCr 8bit data is input.0:EVEN PIXEL 1:ODD PIXEL
10:EXTRG External trigger.0:DIABLE 1:ENABLE
9:TRGSEL Signal that initializes SDRAM address when EXTRG = 1.
0: WEN bit (SYNCEN register).1:FID input port.
8:WENLOG Specifies CCD valid area.
0:Internal valid and WEN signals are ANDed logically.
1:Internal valid and WEN signals are ORed logically.
6:FIDMD Setting of FID detection function.
0:FID signal is latched at the VSYNC 1: FID signal is not latched.
5:BW656 The data width in REC656 input mode. 0:8BIT 1:10BIT
4:YCINSWP Y input (YIN[7:0]) and C input (CIN[7:0]) are swapped.
0:(NO_YCIN_SWAP) YIN[7:0] = Y signal / CIN[7:0] = C signal.
1:(YCIN_SWAP) YIN[7:0] = C signal / CIN[7:0] = Y signal.
15. Start Pixel Horizontal Register (FMTSPH) 针对CFA,即CMYG TO RGBG转换
16. Number Of Pixels Register (FMTLNH) 同上
17. Start Line Vertical Register (FMTSLV) 同上
18. Number of Lines Register (FMTLNV) 同上
19. Lens Shading Correction Configuration 1 Register (LSCCFG1) 同上
20. Lens Shading Correction Configuration 2 Register (LSCCFG2)
21. Lens Shading Correction - Center Position (H0) Register (LSCH0)
22. Lens Shading Correction - Center Position (V0) Register (LSCV0)
23. Lens Shading Correction - Horizontal Coefficients Register (LSCKH)
24. Lens Shading Correction - Vertical Coefficients Register (LSCKV)
25. Lens Shading Correction - Memory Control Register (LSCMEMCTL)
26. Lens Shading Correction - Memory Read Data Register (LSCMEMQ)
27. Defect Correction - Control Register (DFCCTL)
28. Defect Correction - Vertical Saturation Level Register (DFCVSAT)
29. Defect Correction - Memory Control Register (DFCMEMCTL)
30. Defect Correction - Set V Position Register (DFCMEM0)
31. Defect Correction - Set H Position Register (DFCMEM1)
32. Defect Correction - Set SUB1 Register (DFCMEM2)
33. Defect Correction - Set SUB2 Register (DFCMEM3)
34. Defect Correction - Set SUB3 Register (DFCMEM4)
35. Color Space Converter Enable Register (CSCCTL)
36. Color Space Converter - Coefficients #0 Register (CSCM0)-(CSCM7)
37. Data Offset Register (DATAOFST)
15-8 VOFST V direction data offset for defect correction and lens shading correction. Range: 0-255.
7-0 HOFST H direction data offset for defect correction and lens shading Correction. Range: 0-255.
二.IPIPEIF
1. IPIPE I/F Enable Register (ENABLE)
0:ENABLE SDRAM BUFFE读开始信号及产生SYNC信号 ,只有在INPSRC (CFG[3:2]) = 1, 2 or 3.下有用(CFG)
13-11:DATASFT SDRAM Read Data Shift (0_6) 当INPSRC = 1 or 2.有效
0 Output data (13:0) = read data(15:2)
1 Output data (13:0) = read data(14:1)
2 Output data (13:0) = read data(13:0)(
3 Output data (13:0) = read data(12:0) & "0"
4 Output data (13:0) = read data11:0) & "00"
5 Output data (13:0) = read data(10:0) & "000"
6 Output data (13:0) = read data(9:0) & "0000"
2. IPIPE I/F Configuration Register
10: CLKSEL
IPIPEIF & IPIPE Clock Select
This register is available when INPSRC = 1 or 3. Should code "0" when INPSRC = 0 or 2.
0 Pixel clock (PCLK)
1 Divided SDRAM clock as per CLKDIV
9: IALAW Inverse A-law Conversion
Applies inverse A-law (8bit to 10bit) conversion to the SDRAM data.
This register is available when= INPSRC 1 or 2.
0 Inverse alaw off
1 Inverse alaw on
8: PACK8IN 8-Bit Packed Mode INPSRC 1 or 2.有效
0 (NORMAL_16_BITS_PIXEL) 16 bits / pixel
1 (PACK_8_BITS_PIXEL) 8 bits / pixel
7 :AVGFILT Averaging Filter
It applies (1,2,1) filter for the RGB/YCbCr data.
0 Off
1 On
6-4: CLKDIV Clock Selection when Offline Mode (SDRAM Input? Mode)
IPIPEIF/IPIPE clock frequency = CLKDIV x VPSSCLK clock frequency(CLKSEL=1)
0-4:1/2-1/6 5:1/8 6:1/16 7:1/32
3-2: INPSRC CCD/YCbCr Data Port Selection
0 From CCD Controller
1 From SDRAM (raw data)
2 From CCD Controller & SDRAM (Darkframe)
3 From SDRAM (YCbCr data)
1: DECM Pixel Decimation
Decimation rate defined by RSZ register
0 No decimation
1 Decimate
0: ONESHOT One Shot Mode
This register is available when INPSRC = 1 or 3.
0 Continuous mode
1 One shot mode
3. IPIPE I/F Interval of HD / Start pixel in HD Register (PPLN)
4. IPIPE I/F Number of valid pixels per line Register (HNUM)
5. IPIPE I/F Number of Valid Lines per Frame Register (VNUM)
6. IPIPE I/F Memory Address (Upper) Register (ADDRU)
7. IPIPE I/F Memory Address (Lower) Register (ADDRL)
8. IPIPE I/F Address Offset of Each Line Register (ADOFS)
9. IPIPE I/F Horizontal Resizing Parameter Register (RSZ)(当水平像素大于1344时用到）
6-0 RSZ 10h-70h The Horizontal Resizing Parameter 水平RESIZE参数，16到112，以16/RSZ计算
10. IPIPE I/F Gain Parameter Register (GAIN)
三.IPIPE
1. IPIPE Enable Register (IPIPE_EN)
0:EN 在ONE-SHOT模式下,处理完一FRAME后EN自动清0
2. One Shot Mode Register (IPIPE_MODE)
1: WRT CAM_WEN mode selection.WRT=0则不管CAM_WEN,处理每一FRAME;WRT=1,则当CAM_WEN有效时处理(当时序有IPIPEIF产生时,应设为0)
0 ONESHOT One shot mode.
3. Input/Output Data Paths Register (IPIPE_DPATHS)
2 BYPASS Enable RAW-Bypass mode through IPIPE. 当设定时输入影像宽度可以达到4096PIXEL(只当FMT=1有效)
0-1 FMT Data Path through IPIPE.
0 (RAW2YUV) Bayer input, YCbCr (or RGB) output.
1 (RAW2RAW) Bayer input, Bayer output.
2 (RAW2BOX) Bayer input, Boxcar output.
3 (YUV2YUV) YCbCr (16bit) input, YCbCr (or RGB) output
4. Color Pattern Register (IPIPE_COLPAT)
5. Vertical Start Position Register (IPIPE_VST)
6. Vertical Processing Size Register (IPIPE_VSZ)
7. Horizontal Start Position Register (IPIPE_HST)
8. Horizontal Processing Size Register (IPIPE_HSZ)
9. ARM Gated Clock Control Register (GCL_ARM)
0 REG IPIPE MMR clock enable.
The on/off selection of the MMR interface clock which is used for ARM register accesses.
0 Off
1 On
10. CCD Gated Clock Control Register (GCL_CCD)
2 G2 IPIPE G2 clock enable.
The on/off selection of the clock which is used for the IPIPE processing of "CFA" to "422", "Histogram".
0 Off
1 On
1 G1 IPIPE G1 clock enable.
The on/off selection of the clock which is used for the IPIPE processing of "Defect Correction" to "WhiteBalance".
0 Off
1 On
0 G0 IPIPE G0 clock enable.
The on/off selection of the clock which is used for the IPIPE processing of "Boxcar".
0 Off
1 On
11. SDR Gated Clock Control Register (GCL_SDR)(RESIZER模块时钟能动，当为0时在RESIZER BYPASS模式）
0 RSZ IPIPE RSZ clock enable.
The on/off selection of the clock which is used for "Resize". The resizer operates in bypass mode when
this is off.
0 Off
1 On
12. Internal Table Selection Register (RAM_MODE)
13. Address Register (RAM_ADR)
14. Write Data Register (RAM_WDT)
15. Read Data Register (RAM_RDT)
16. Interrupt Enable Register (IRQ_EN)
17. Interval of IRQ-2 Register (IRQ_RZA)
12-0 VAL 0-1FFFh Interval of IRQ_2. Interrupt signal at every (VAL + 1) lines of Resize and RGB output.
18. Interval of IRQ-3 Register (IRQ_RZB)
12-0 VAL 0-1FFFh Interval of IRQ_3. Interrupt signal at every (VAL + 1) lines of Resize and RGB output
19. Defect Correction Enable Register (DFC_EN)
20. Copy Method Selection (from Top or from Bottom) Register (DFC_SEL)
21. Start Address in LUT Register (DFC_ADR)
22. Number of Available Entries in LUT Register (DFC_SIZ)
23. 2D Noise Filter Enable Register (D2F_EN)
24. Noise Filter Configuration Register (D2F_CFG)
25. Noise Filter LUT Values (Threshold) Register (D2F_THR[32])
26. Noise Filter LUT Values (Intensity) Register (D2F_STR[32])
27. PreFilter Enable Register (PRE_EN)
28. PreFilter Type Register (PRE_TYP)
29. Shift Value of Adaptive Gain Register (PRE_SHF)
30. Constant Gain or Adaptive Gain Slope Register (PRE_GAIN)
31. Threshold G Register (PRE_THR_G)
32. Threshold B Register (PRE_THR_B)
33. Threshold 1 Register (PRE_THR_1)
34. Digital Gain Register (WB2_DGN)
35. White Balance Gain Register (WB2_WG_R),(WB2_WG_GR),(WB2_WG_GB)(WB2 _WG_B)
36. Matrix Coefficient RR Register (RGB_MUL_RR),RGB_MUL_GR,RGB_MUL_BR),(RGB_MUL_RG)
37. Matrix Coefficient GG Register (RGB_MUL_GG),(RGB_MUL_BG),(RGB_MUL_RB),(RGB_MUL_GB),(RGB_MUL_BB)
38. R Output Offset Register (RGB_OFT_OR),(RGB_OFT_OG),(RGB_OFT_OB)
39. Gamma Correction Configuration Register (GMM_CFG)
40. Luminance Adjustment (Contrast and Brightness) Register (YCC_ADJ)
41. Matrix Coefficient RY Register (YCC_MUL_RY),(YCC_MUL_GY),(YCC_MUL_BY),(YCC_MUL_RCB),(YCC_MUL_GCB),(YCC_MUL_BCB),(YCC_MUL_RCR),(YCC_MUL_GCR),(YCC_MUL_BCR)
42. Y Output Offset Register (YCC_OFT_Y)
43. Cb Output Offset Register (YCC_OFT_CB)
44. Cr Output Offset Register (YCC_OFT_CR)
45. Saturation (Luminance Minimum) Register (YCC_Y_MIN)
46. Saturation (Luminance Maximum) Register (YCC_Y_MAX)
47. Saturation (Chrominance Minimum) Register (YCC_C_MIN)
48. Saturation (Chrominance Maximum) Register (YCC_C_MAX)
49. Chrominance Position (for 422 Down Sampler) Register (YCC_PHS)(当输入为YCBCR时）
50. Edge Enhancer Enable Register (YEE_EN)
51. MedianNR Enable Register (YEE_EMF)
52. HPF Shift Length Register (YEE_SHF)
53. HPF Coefficient 00 Register (YEE_MUL_00，01，02，10，11，12，20，21，22)
54. Fault Color Suppression Enable Register (FCS_EN)
55. Type selection of HPF Register (FCS_TYP)
56. Down Shift Size (HPF) Register (FCS_SHF_Y)
57. Down Shift Size (GAIN) Register (FCS_SHF_C)
58. Threshold Register (FCS_THR)
59. Intensity Register (FCS_SGN)
60. Processing Mode Register (RSZ_SEQ)
4 CRV Chroma sampling point change.
0 Chroma sampling point is not changed.
1 Chroma sampling point is changed from odd-numbered pixels to even-number pixels. The pixel the leftend is removed and the pixel at the right end is duplicated.
3 VRV Vertical reversal of output image.
0 Processed lines are output in the order of input (normal operation) in vertical direction.
1 The order of output data is flipped top to bottom.
2 HRV Horizontal reversal of output image.
0 Processed pixels are output in the order of input (normal operation) in horizontal direction.
1 The order of output data is flipped left to right.
1 TMM Terminal condition of vertical processing.
0 Output line number confined mode (normal mode). The module continues output of resized image untilthe number of output lines reaches the value set by RZA_O_VSZ and RZB_O_VSZ.
1 Input line number confined mode. The modules continues output of resized image until the inputnumber of input lines reads the value set by RZA_I_VSZ and RZB_I_VSZ. The numbers of output linesare output to RZA_V_SIZ_O and RZB_V_SIZ_O.
0 SEQ Operation mode of vertical processing.
0 Normal mode. The module clears register values and internal buffer values at VSYNC.
1 Continuous mode. Resizer holds values from the previous operation. This mode may only be used incombination with input line number confined mode (TMM=1).
61. Vertical Anti aliasing Filter Register (RSZ_AAL)
62. Resizer Enable Register (RSZ_EN)
63. One Shot Mode Register (RSZ_MODE)
0 OST One shot mode enable.
0 Continuous mode.
1 One shot mode.
64. Vertical Start Position of the Input Register (RSZ_I_VST)
11-0 VAL 0-FFFh Vertical start position of image processing.
After IPIPE_VST, the VAL line is processed as the first line in each image.(在IPIPE_VST之后计算)
65. Vertical Size of the Input Register (RSZ_I_VSZ)
11-0 VAL 0-FFFh Number of input lines. This value is used only in input line confined mode.(RSZ_SEQ[TMM] at 0108h).
The number of input lines is (VAL + 1).
66. Horizontal Start Position of the Input Register (RSZ_I_HST)
11-0 VAL 0-FFFh Horizontal start position of image processing.
(RSZ_I_HST[0] is held low so this value must be even). After IPIPE_HST, the VAL pixel is
processed as the first pixel.
67. Vertical Size of the Output Register (RSZ_O_VSZ)
11-0 VAL 0-FFFh Vertical size of the output image.
The number of output lines is (VAL + 1). (RSZ_O_VSZ[0] is held high so this value must be odd).
68. Horizontal Start Position of the Output Register (RSZ_O_HST)
11-0 VAL 0-FFFh Horizontal position of the first pixel to be output in processed image.
The first VAL pixels of the resized area in each line are discarded, and the next pixel becomes the first
to be output. (RSZ_O_HST[0] is held low so this value must be even).
69. Horizontal Size of the Output Register (RSZ_O_HSZ)
11-0 VAL 0-FFFh Horizontal size of output image. The number of pixel in each line is (VAL + 1).
RSZ[0]:Value must be lower than 1344 except in RAW passthu mode.
RSZ[1]:Value must be lower than 640. (RSZ_O_HSZ[0] is held high so this value must be odd).
70. Initial Phase of Vertical Resizing Process Register (RSZ_V_PHS)
13-0 VAL 0-3FFFh Initial value for the phase value in vertical resizing process. (Should be set to zero except in Frame
Division Mode-H). Valid range: 0-8191.
71. Phase of Last Value in Previous Resize Process Register (RSZ_V_PHS_O)
13-0 VAL 0-3FFFh Phase value of the last line in the previous resizing process. This value is only valid in input line
number confined mode ((RSZ_SEQ[TMM] at 0x0108).
72. Vertical Resize Parameter Register (RSZ_V_DIF)
13-0 VAL 0-3FFFh Vertical resize parameter. The actual resizing ratio is 256/VAL.
73. Actual Number of Output Lines Register (RSZ_V_SIZ_O)
12-0 VAL 0-1FFFh Number of actually produced lines in the previous resizing process
74. Initial Phase of Horizontal Resizing Process Register (RSZ_H_PHS)
一.CCDC
1.Synchronization Enable Register (SYNCEN)
0:VDHDEN
1:WEN
2.MODESET
15:FLDSTAT 0:ODD FIELD 1:EVEN FIELD
14:LPF 3-tap Low-Pass (anti-aliasing) filter for ccd data 0:off 1:on
13-12:INPMOD INPUT MODE 0:CCD RAW DATA 1:YCBCR 16BIT 2:YCBCR 8BIT
11:PACK8 0:NORMAL 16BIT TO SDRAM 1:PACK8 BIT TO SDRAM
10-8:DATASFT 0:NO SHIFT 1-6:SHIFT 1-6BIT
7:FLDMODE 0:NON-INTERFACED 1：INTERFACED （若EXWEN =1，则需为0）
6:DATAPOL 0:NORMAL 1:ONE'S CONPLEMENT
5:EXWEN 0:不用外部WEN 1:用外部VD/HD作为写SDRAM的信号
4:FLDPOL 0:POSITIVE 1:NEGATIVE
3:HDPOL 意思同上
2:VDPOL 意思同上
0:VDHDOUT 0:VD,HD INPUT 1:VD,HD OUTPUT
3. Horizontal Size Register (HSIZE)
12:ADR_UPDT SDRAM 地址更新方式0:自动增加 1:自动减少
11-0:LNOFST SDRAM中行尺寸,32BYTE为单位即16或32PIXELS
4.SDRAM Line Offset Register (SDOFST)
14：FIINV 0：NON INVERSE 1：INVERSE
13-12：FOFST Line offset value of odd field (FID = 1) 0-3：+1 - +4
11-9：LOFST0 Line offset values of even line and even field (FID = 0) 0-7：+1 - -4
8-6：LOFST1 Line offset values of odd line and even field (FID = 0) 同上
5-3：LOFST2 Line offset values of even line and odd field (FID = 1) 同上
2-0：LOFST3 Line offset values of odd line and odd field (FID = 1)同上
5.SDRAM Address - High Register (STADRH)
6.SDRAM Address - LOW Register (STADRL)
7.CCD Color Pattern Register (COLPTN)
8. CCD Gain Adjustment - R/Ye Register (RYEGAIN)
CCD Gain Adjustment - Gr/Cy Register (GRCYGAIN)
CCD Gain Adjustment - Gb/G Register (GBGGAIN)
CCD Gain Adjustment - B/Mg Register (BMGGAIN)
CCD Offset Adjustment Register (OFFSET)
9.Output Clipping Value Register (OUTCLIP)
10.VD Interrupt #0 Register (VDINT0) 中断设定行数
11. VD Interrupt #1 Register (VDINT1)
12. Gamma Correction Settings Register (GAMMAWD)
11-10:MFIL1 Median filter mode for IPIPE 0:no filer 1:average filer 2:median filer
9-8: MFIL1 Median Filter for SDRAM capture.值同上
5：CFAP CFA Pattern. 0：Mosaic 1：Stripe
4-2：GWDI Gamma Width Input (For A-LAW table & H3A port)
0：BITS 13-4 1：12-3 2：11-2 3：10-1 4：9-0
0：CCDTBL Apply Gamma (A-LAW) to CCDC data saved to SDRAM 0：DISABLE 1：ENABLE
13. REC656 Control Register (REC656IF)
1: ECCFVH FVH error correction enable 0:DISABLE 1:ENABLE
0: R656ON REC656 interface enable 0:DISABLE 1:ENABLE
14. CCD Configuration Register (CCDCFG)
15:VDLC Enable synchronizing function regs on VSYNC. 0:Latched on VSYNC. 1:NO LATCHED
13:MSBINVI MSB of Chroma input signal stored to SDRAM inverted.0:NORMAL 1:MSB INVERTED
12:BSWD Byte swap data stored to SDRAM. 0:NORMAL 1:BYTE SWAP
11:Y8POS Location of Y signal when YCbCr 8bit data is input.0:EVEN PIXEL 1:ODD PIXEL
10:EXTRG External trigger.0:DIABLE 1:ENABLE
9:TRGSEL Signal that initializes SDRAM address when EXTRG = 1.
0: WEN bit (SYNCEN register).1:FID input port.
8:WENLOG Specifies CCD valid area.
0:Internal valid and WEN signals are ANDed logically.
1:Internal valid and WEN signals are ORed logically.
6:FIDMD Setting of FID detection function.
0:FID signal is latched at the VSYNC 1: FID signal is not latched.
5:BW656 The data width in REC656 input mode. 0:8BIT 1:10BIT
4:YCINSWP Y input (YIN[7:0]) and C input (CIN[7:0]) are swapped.
0:(NO_YCIN_SWAP) YIN[7:0] = Y signal / CIN[7:0] = C signal.
1:(YCIN_SWAP) YIN[7:0] = C signal / CIN[7:0] = Y signal.
15. Start Pixel Horizontal Register (FMTSPH) 针对CFA,即CMYG TO RGBG转换
16. Number Of Pixels Register (FMTLNH) 同上
17. Start Line Vertical Register (FMTSLV) 同上
18. Number of Lines Register (FMTLNV) 同上
19. Lens Shading Correction Configuration 1 Register (LSCCFG1) 同上
20. Lens Shading Correction Configuration 2 Register (LSCCFG2)
21. Lens Shading Correction - Center Position (H0) Register (LSCH0)
22. Lens Shading Correction - Center Position (V0) Register (LSCV0)
23. Lens Shading Correction - Horizontal Coefficients Register (LSCKH)
24. Lens Shading Correction - Vertical Coefficients Register (LSCKV)
25. Lens Shading Correction - Memory Control Register (LSCMEMCTL)
26. Lens Shading Correction - Memory Read Data Register (LSCMEMQ)
27. Defect Correction - Control Register (DFCCTL)
28. Defect Correction - Vertical Saturation Level Register (DFCVSAT)
29. Defect Correction - Memory Control Register (DFCMEMCTL)
30. Defect Correction - Set V Position Register (DFCMEM0)
31. Defect Correction - Set H Position Register (DFCMEM1)
32. Defect Correction - Set SUB1 Register (DFCMEM2)
33. Defect Correction - Set SUB2 Register (DFCMEM3)
34. Defect Correction - Set SUB3 Register (DFCMEM4)
35. Color Space Converter Enable Register (CSCCTL)
36. Color Space Converter - Coefficients #0 Register (CSCM0)-(CSCM7)
37. Data Offset Register (DATAOFST)
15-8 VOFST V direction data offset for defect correction and lens shading correction. Range: 0-255.
7-0 HOFST H direction data offset for defect correction and lens shading Correction. Range: 0-255.
二.IPIPEIF
1. IPIPE I/F Enable Register (ENABLE)
0:ENABLE SDRAM BUFFE读开始信号及产生SYNC信号 ,只有在INPSRC (CFG[3:2]) = 1, 2 or 3.下有用(CFG)
13-11:DATASFT SDRAM Read Data Shift (0_6) 当INPSRC = 1 or 2.有效
0 Output data (13:0) = read data(15:2)
1 Output data (13:0) = read data(14:1)
2 Output data (13:0) = read data(13:0)(
3 Output data (13:0) = read data(12:0) & "0"
4 Output data (13:0) = read data11:0) & "00"
5 Output data (13:0) = read data(10:0) & "000"
6 Output data (13:0) = read data(9:0) & "0000"
2. IPIPE I/F Configuration Register
10: CLKSEL
IPIPEIF & IPIPE Clock Select
This register is available when INPSRC = 1 or 3. Should code "0" when INPSRC = 0 or 2.
0 Pixel clock (PCLK)
1 Divided SDRAM clock as per CLKDIV
9: IALAW Inverse A-law Conversion
Applies inverse A-law (8bit to 10bit) conversion to the SDRAM data.
This register is available when= INPSRC 1 or 2.
0 Inverse alaw off
1 Inverse alaw on
8: PACK8IN 8-Bit Packed Mode INPSRC 1 or 2.有效
0 (NORMAL_16_BITS_PIXEL) 16 bits / pixel
1 (PACK_8_BITS_PIXEL) 8 bits / pixel
7 :AVGFILT Averaging Filter
It applies (1,2,1) filter for the RGB/YCbCr data.
0 Off
1 On
6-4: CLKDIV Clock Selection when Offline Mode (SDRAM Input? Mode)
IPIPEIF/IPIPE clock frequency = CLKDIV x VPSSCLK clock frequency(CLKSEL=1)
0-4:1/2-1/6 5:1/8 6:1/16 7:1/32
3-2: INPSRC CCD/YCbCr Data Port Selection
0 From CCD Controller
1 From SDRAM (raw data)
2 From CCD Controller & SDRAM (Darkframe)
3 From SDRAM (YCbCr data)
1: DECM Pixel Decimation
Decimation rate defined by RSZ register
0 No decimation
1 Decimate
0: ONESHOT One Shot Mode
This register is available when INPSRC = 1 or 3.
0 Continuous mode
1 One shot mode
3. IPIPE I/F Interval of HD / Start pixel in HD Register (PPLN)
4. IPIPE I/F Number of valid pixels per line Register (HNUM)
5. IPIPE I/F Number of Valid Lines per Frame Register (VNUM)
6. IPIPE I/F Memory Address (Upper) Register (ADDRU)
7. IPIPE I/F Memory Address (Lower) Register (ADDRL)
8. IPIPE I/F Address Offset of Each Line Register (ADOFS)
9. IPIPE I/F Horizontal Resizing Parameter Register (RSZ)(当水平像素大于1344时用到）
6-0 RSZ 10h-70h The Horizontal Resizing Parameter 水平RESIZE参数，16到112，以16/RSZ计算
10. IPIPE I/F Gain Parameter Register (GAIN)
三.IPIPE
1. IPIPE Enable Register (IPIPE_EN)
0:EN 在ONE-SHOT模式下,处理完一FRAME后EN自动清0
2. One Shot Mode Register (IPIPE_MODE)
1: WRT CAM_WEN mode selection.WRT=0则不管CAM_WEN,处理每一FRAME;WRT=1,则当CAM_WEN有效时处理(当时序有IPIPEIF产生时,应设为0)
0 ONESHOT One shot mode.
3. Input/Output Data Paths Register (IPIPE_DPATHS)
2 BYPASS Enable RAW-Bypass mode through IPIPE. 当设定时输入影像宽度可以达到4096PIXEL(只当FMT=1有效)
0-1 FMT Data Path through IPIPE.
0 (RAW2YUV) Bayer input, YCbCr (or RGB) output.
1 (RAW2RAW) Bayer input, Bayer output.
2 (RAW2BOX) Bayer input, Boxcar output.
3 (YUV2YUV) YCbCr (16bit) input, YCbCr (or RGB) output
4. Color Pattern Register (IPIPE_COLPAT)
5. Vertical Start Position Register (IPIPE_VST)
6. Vertical Processing Size Register (IPIPE_VSZ)
7. Horizontal Start Position Register (IPIPE_HST)
8. Horizontal Processing Size Register (IPIPE_HSZ)
9. ARM Gated Clock Control Register (GCL_ARM)
0 REG IPIPE MMR clock enable.
The on/off selection of the MMR interface clock which is used for ARM register accesses.
0 Off
1 On
10. CCD Gated Clock Control Register (GCL_CCD)
2 G2 IPIPE G2 clock enable.
The on/off selection of the clock which is used for the IPIPE processing of "CFA" to "422", "Histogram".
0 Off
1 On
1 G1 IPIPE G1 clock enable.
The on/off selection of the clock which is used for the IPIPE processing of "Defect Correction" to "WhiteBalance".
0 Off
1 On
0 G0 IPIPE G0 clock enable.
The on/off selection of the clock which is used for the IPIPE processing of "Boxcar".
0 Off
1 On
11. SDR Gated Clock Control Register (GCL_SDR)(RESIZER模块时钟能动，当为0时在RESIZER BYPASS模式）
0 RSZ IPIPE RSZ clock enable.
The on/off selection of the clock which is used for "Resize". The resizer operates in bypass mode when
this is off.
0 Off
1 On
12. Internal Table Selection Register (RAM_MODE)
13. Address Register (RAM_ADR)
14. Write Data Register (RAM_WDT)
15. Read Data Register (RAM_RDT)
16. Interrupt Enable Register (IRQ_EN)
17. Interval of IRQ-2 Register (IRQ_RZA)
12-0 VAL 0-1FFFh Interval of IRQ_2. Interrupt signal at every (VAL + 1) lines of Resize and RGB output.
18. Interval of IRQ-3 Register (IRQ_RZB)
12-0 VAL 0-1FFFh Interval of IRQ_3. Interrupt signal at every (VAL + 1) lines of Resize and RGB output
19. Defect Correction Enable Register (DFC_EN)
20. Copy Method Selection (from Top or from Bottom) Register (DFC_SEL)
21. Start Address in LUT Register (DFC_ADR)
22. Number of Available Entries in LUT Register (DFC_SIZ)
23. 2D Noise Filter Enable Register (D2F_EN)
24. Noise Filter Configuration Register (D2F_CFG)
25. Noise Filter LUT Values (Threshold) Register (D2F_THR[32])
26. Noise Filter LUT Values (Intensity) Register (D2F_STR[32])
27. PreFilter Enable Register (PRE_EN)
28. PreFilter Type Register (PRE_TYP)
29. Shift Value of Adaptive Gain Register (PRE_SHF)
30. Constant Gain or Adaptive Gain Slope Register (PRE_GAIN)
31. Threshold G Register (PRE_THR_G)
32. Threshold B Register (PRE_THR_B)
33. Threshold 1 Register (PRE_THR_1)
34. Digital Gain Register (WB2_DGN)
35. White Balance Gain Register (WB2_WG_R),(WB2_WG_GR),(WB2_WG_GB)(WB2 _WG_B)
36. Matrix Coefficient RR Register (RGB_MUL_RR),RGB_MUL_GR,RGB_MUL_BR),(RGB_MUL_RG)
37. Matrix Coefficient GG Register (RGB_MUL_GG),(RGB_MUL_BG),(RGB_MUL_RB),(RGB_MUL_GB),(RGB_MUL_BB)
38. R Output Offset Register (RGB_OFT_OR),(RGB_OFT_OG),(RGB_OFT_OB)
39. Gamma Correction Configuration Register (GMM_CFG)
40. Luminance Adjustment (Contrast and Brightness) Register (YCC_ADJ)
41. Matrix Coefficient RY Register (YCC_MUL_RY),(YCC_MUL_GY),(YCC_MUL_BY),(YCC_MUL_RCB),(YCC_MUL_GCB),(YCC_MUL_BCB),(YCC_MUL_RCR),(YCC_MUL_GCR),(YCC_MUL_BCR)
42. Y Output Offset Register (YCC_OFT_Y)
43. Cb Output Offset Register (YCC_OFT_CB)
44. Cr Output Offset Register (YCC_OFT_CR)
45. Saturation (Luminance Minimum) Register (YCC_Y_MIN)
46. Saturation (Luminance Maximum) Register (YCC_Y_MAX)
47. Saturation (Chrominance Minimum) Register (YCC_C_MIN)
48. Saturation (Chrominance Maximum) Register (YCC_C_MAX)
49. Chrominance Position (for 422 Down Sampler) Register (YCC_PHS)(当输入为YCBCR时）
50. Edge Enhancer Enable Register (YEE_EN)
51. MedianNR Enable Register (YEE_EMF)
52. HPF Shift Length Register (YEE_SHF)
53. HPF Coefficient 00 Register (YEE_MUL_00，01，02，10，11，12，20，21，22)
54. Fault Color Suppression Enable Register (FCS_EN)
55. Type selection of HPF Register (FCS_TYP)
56. Down Shift Size (HPF) Register (FCS_SHF_Y)
57. Down Shift Size (GAIN) Register (FCS_SHF_C)
58. Threshold Register (FCS_THR)
59. Intensity Register (FCS_SGN)
60. Processing Mode Register (RSZ_SEQ)
4 CRV Chroma sampling point change.
0 Chroma sampling point is not changed.
1 Chroma sampling point is changed from odd-numbered pixels to even-number pixels. The pixel the leftend is removed and the pixel at the right end is duplicated.
3 VRV Vertical reversal of output image.
0 Processed lines are output in the order of input (normal operation) in vertical direction.
1 The order of output data is flipped top to bottom.
2 HRV Horizontal reversal of output image.
0 Processed pixels are output in the order of input (normal operation) in horizontal direction.
1 The order of output data is flipped left to right.
1 TMM Terminal condition of vertical processing.
0 Output line number confined mode (normal mode). The module continues output of resized image untilthe number of output lines reaches the value set by RZA_O_VSZ and RZB_O_VSZ.
1 Input line number confined mode. The modules continues output of resized image until the inputnumber of input lines reads the value set by RZA_I_VSZ and RZB_I_VSZ. The numbers of output linesare output to RZA_V_SIZ_O and RZB_V_SIZ_O.
0 SEQ Operation mode of vertical processing.
0 Normal mode. The module clears register values and internal buffer values at VSYNC.
1 Continuous mode. Resizer holds values from the previous operation. This mode may only be used incombination with input line number confined mode (TMM=1).
61. Vertical Anti aliasing Filter Register (RSZ_AAL)
62. Resizer Enable Register (RSZ_EN)
63. One Shot Mode Register (RSZ_MODE)
0 OST One shot mode enable.
0 Continuous mode.
1 One shot mode.
64. Vertical Start Position of the Input Register (RSZ_I_VST)
11-0 VAL 0-FFFh Vertical start position of image processing.
After IPIPE_VST, the VAL line is processed as the first line in each image.(在IPIPE_VST之后计算)
65. Vertical Size of the Input Register (RSZ_I_VSZ)
11-0 VAL 0-FFFh Number of input lines. This value is used only in input line confined mode.(RSZ_SEQ[TMM] at 0108h).
The number of input lines is (VAL + 1).
66. Horizontal Start Position of the Input Register (RSZ_I_HST)
11-0 VAL 0-FFFh Horizontal start position of image processing.
(RSZ_I_HST[0] is held low so this value must be even). After IPIPE_HST, the VAL pixel is
processed as the first pixel.
67. Vertical Size of the Output Register (RSZ_O_VSZ)
11-0 VAL 0-FFFh Vertical size of the output image.
The number of output lines is (VAL + 1). (RSZ_O_VSZ[0] is held high so this value must be odd).
68. Horizontal Start Position of the Output Register (RSZ_O_HST)
11-0 VAL 0-FFFh Horizontal position of the first pixel to be output in processed image.
The first VAL pixels of the resized area in each line are discarded, and the next pixel becomes the first
to be output. (RSZ_O_HST[0] is held low so this value must be even).
69. Horizontal Size of the Output Register (RSZ_O_HSZ)
11-0 VAL 0-FFFh Horizontal size of output image. The number of pixel in each line is (VAL + 1).
RSZ[0]:Value must be lower than 1344 except in RAW passthu mode.
RSZ[1]:Value must be lower than 640. (RSZ_O_HSZ[0] is held high so this value must be odd).
70. Initial Phase of Vertical Resizing Process Register (RSZ_V_PHS)
13-0 VAL 0-3FFFh Initial value for the phase value in vertical resizing process. (Should be set to zero except in Frame
Division Mode-H). Valid range: 0-8191.
71. Phase of Last Value in Previous Resize Process Register (RSZ_V_PHS_O)
13-0 VAL 0-3FFFh Phase value of the last line in the previous resizing process. This value is only valid in input line
number confined mode ((RSZ_SEQ[TMM] at 0x0108).
72. Vertical Resize Parameter Register (RSZ_V_DIF)
13-0 VAL 0-3FFFh Vertical resize parameter. The actual resizing ratio is 256/VAL.
73. Actual Number of Output Lines Register (RSZ_V_SIZ_O)
12-0 VAL 0-1FFFh Number of actually produced lines in the previous resizing process
74. Initial Phase of Horizontal Resizing Process Register (RSZ_H_PHS)
VPFE寄存器说明
VPFE
1.OVERVIEW
1.1 CCDC
1）产生SD，HD时序信号
2）可编程镜头阴影校正（ Lens Shading Correction）.
3）支持BT656，YCBCR422（8BIT，16BIT，WITH HS，VS），及14BIT RAW DATA FROM CCD/CMOS
4) 可编程14BIT 到8BIT输出
5）可通过外部写能动信号EN控制向DDR写数据
6）SENSOR CLK可达75MHZ，若用到H3A，则只能达67.5MHZ
7）DEFECT CORRECT
1.2.H3A
1）auto white balance and auto eexposure by collecting metrics（统计）
2）读写DDR
3）只接收RAW DATA
1.3.IPIPE
1）只接收RAW DATA ，且转换14BIT RAW DATA为YCBCR422或YCRCR422 RESIZE
2）支持RGB Bayer pattern，经过彩色空间转换也支持CMYG
3）每个分量增益控制
4）可编程的RGB TO YCBCR的转换系数
5）可配置成仅RESIZE模式，即直接YCBCR422 RESIZE，不经过其它模块处理
6）RGB (32bit/16bit) output to SDRAM
7）要求至少BLANK 8PIXEL/行，4行 BLANK，在ONE SHOT 下，至少10行 BLANK，在处理之后
8）最大支持1344PIXEL 输入输出宽度
9）DEFECT CORRECT
1.4.IPIPEIF
1）读CCDC，SDRAM，写IPIPE
2）重新调整 HD, VD, and PCLK timing to the IPIPE input.
3）dark-frame subtract黑色帧消除法降噪（用于长时间瀑光引起的噪声点）
2.引脚IO 接口
1. YIN[7..0]/CCDIN[7..0]
2. CIN[5..0]/CCDIN[13..0]
3.PCLK
4.CAM_HD,CAM_VD
5.CAM_WEN_FIELD:/设 CCD Write Enable/Field ID signal
1）作FIELD标识信号，FLDMODE定类型提供，由CCD/CMOSFIDMD/FLDPOL
2）作WEN用，EXWEN打开，WENLOG设定AND 或 OR，与在SPH, NPH, SLV, NLV内的有效像素相AND或OR
RAM模式引脚:
以上全需用到
另少于14BIT时,一般用CCD[13..0]高位,舍去底位,当用时SPI时除外
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引脚配置REG: PINMUX0(VPFE.PDF PAGE38)
3。VPFE/ISP Integration
VPSS Events:9个作为中断送ARM，4个作为EVENT送EDMA
Number Acronym Module Description
0 CCDC VDINT0 CCDC Triggered after a programmable number of input lines for each frame.
1 CCDC VDINT1 CCDC Triggered after a programmable number of input lines for each frame.
2 CCDC VDINT2 CCDC Triggered at the rising edge of WEN signal
3 H3AINT H3A Triggered at the end of AF or AEW writes to DDR for each frame
4 VENCINT VENC Triggered at the rising edge of VSYNC
5 OSDINT OSD Triggered at the end of each frame read from DDR
6 IPIPEIFINT IPIPEIF Triggered at the rising edge of VD if enabled
7 IPIPE_INT0_HST IPIPE Triggered when Histogram processing is finished for each frame
8 IPIPE_INT1_SDR IPIPE Triggered when writes to DDR are finished for each frame
9 IPIPE_INT2_RZA IPIPE Triggered when the number of lines programmed has been output of RZA
10 IPIPE_INT3_RZB IPIPE Triggered when the number of lines programmed has been output of RZB
12 IPIPE_INT5_MMR IPIPE Triggered when MMR modifications for the next frame can be made
中断：VPSSBL.INTSEL选择
INT Number Acronym
0 VPSSINT0
1 VPSSINT1
2 VPSSINT2
3 VPSSINT3
4 VPSSINT4
5 VPSSINT5
6 VPSSINT6
7 VPSSINT7
8 VPSSINT8
事件：VPSSBL.EVTSEL选择
Event Number Binary Event Name
4 0000100 VPSSEVT1
5 0000101 VPSSEVT2
6 0000110 VPSSEVT3
7 0000111 VPSSEVT4
VPSS REG：
VPFE Module Register Map
VPSS Registers Address Range Size
VPSSCLK 0x01C70000 0x01C7007F 128B
H3A 0x01C70080 0x01C700FF 128B
IPIPEIF 0x01C70100 0x01C701FF 256B
OSD 0x01C70200 0x01C702FF 256B
VENC 0x01C70400 0x01C705FF 512B
CCDC 0x01C70600 0x01C707FF 512B
VPSSBL 0x01C70800 0x01C708FF 256B
IPIPE 0x01C71000 0x01C73FFF 12K-
-------------------------------------------------------------------------
4 。VPFE/ISP Functional Description
4.1 CCDC
参数：MODESET.INPMOD输出到DDR的数据选择，YCBCR或RGB
RAW模式时序参数：HDW，VDW，PPLN，HLPFR （从AFE来）
RAW模式时CCDCFG.YCINSWP=0
4.1.2.1 DIGITAL CLAMP
CLAMP的黑电平可用常量也可从像素中计算得到,也可从CCD SENSOR的上黑边，左黑边提取基量
以求平均值计算。
参数：CLAMP.OBST 黑像素开始点；CLAMP.OBSLEN每行的用来求平均的像素数；DCSUB.OBSLN求平均的行数
4.1.2.2 Color Space Conversion
CSCCTL[0]开启。由乘加器，LINE MEMORY组成，CMYG--》RGBG
FMTSPH, FMTLNH, FMTSLV, and FMTLNV指定数据区域
转换后数据会有一行LATENCY（延迟）。
最后一行至少要有一无效像素，一FRAME中至少要有一无效行
4.1.2.3 Defect Correction：坏点校正
DFCCTL[0]开启，可校正1024个点
4.1.2.4 Lens Shading Correction：镜头阴影校正
LSCCFG[0]开启，由于镜头中心较亮，向边缘渐暗。由此而校正
4.1.2.5 Black Level Compensation：太亮，太暗补偿
BLKCMP0.R_YE, BLKCMP0.GR_CY, BLKCMP1.GB_G, BLKCMP1.B_MG)
4.1.2.6 Median Filter：中央滤波。一路送SDRAM，另一路送IPIPE，可单独能动
1. Average Filter Configuration
2. Median Filter Configuration
GAMMAWD.MFILT1 and GAMMAWD.MFILT2
4.1.2.7 SDRAM RAW Output Formatting
4.1.4 Data Output Control
• SDOFST.FIINV – invert interpretation of the Field ID signal
• SDOFST.FIINV – invert interpretation of the Field ID signal
• SDOFST.LOFTS0 – offset, in lines, between even lines on even fields (field 0)
• SDOFST.LOFTS1 – offset, in lines, between odd lines on even fields (field 0)
• SDOFST.LOFTS2 – offset, in lines, between even lines on odd fields (field 1)
• SDOFST.LOFTS3 – offset, in lines, between odd lines on odd fields (field 1)
4.2 IPIPEIF
参数：HDW=8PIXEL，VDW=4LINE（CONTINUE）OR 10LINE（ONE SHOT），PPLN=HD 间隔，LPFR=VD 间隔>1 LINE，HNUM=水平有效像素（从HD上升沿开始？？？），VNUM=垂直有效像素（从VD下降沿开始，即隔4或10LINE）
4.2.1.1 CCDC RAW Input Mode (CFG.INPSRC = 0)
14BIT
4.2.1.2 SDRAM RAW Input Mode (CFG.INPSRC = 1h)
从SDRAM中读取8BIT或16BIT，8BIT为经过A-LAW压缩的，可设CFG.IALAW解压，也可填0补齐
4.2.1.3 CCDC RAW Input With Dark Frame Subtract From SDRAM Mode (CFG.INPSRC = 2h)
IPIPEIF INPUT = CCDC RAW INPUT - SDRAM INPUT
此时PPLN，LPFR的意义与其它输入模式不同，表示从CCDC DATA中减去时的水平，垂直方向的起始位置
4.2.1.4 SDRAM YCbCr 4:2:2 Input Mode (CFG.INPSRC = 3h)
16BIT YCbCr 4:2:2 data
4.2.2 时序产生
当输入为0或2时，HD/VD/WEN ，PCLK由CCDC提供， 为1或3时，IPIEIF产生HD/VD（基于LPFR and PPLN），PCLK可继续用CCDC的PCLK（CFG.CLKSEL=0），也可自已产生（CFG.CLKSEL=1）（用VPSSCLK分频CFG.CLKDIV），产生PCLK时要考虑下面IPIPE RESIZE时最大时钟要求及SDRAM实时操作要求
当CFG.INPSRC非0时，IPIPE I/F SDRAM data读及时序产生即可在ONE-SHOT 下，也可在CONTINUE模式下（(ENABLE.ENABLE）
当输入大于1344PIXEL时开启CFG.DECM设定比例系数以缩小到1344以下
4.3 IPIPE
参数：IPIPE_HST,IPIPE_VST定义开始点（与HD，VD上升沿为原点），IPIPE_HSZ, IPIPE_VSZ定义要处理的数据区域大小
IPIPE_COLPAT定义处理数据的Color pattern
Input Modes (IPIPE_DPATHS.FMT)
0: RAW to YCbCr
1: RAW to RAW
2: RAW to Boxcar
3: YCbCr to YCbCr
In RAW pass through mode,可以支持最大4096PIXEL/LINE，直接写到SDRAM
4.3.3 Defect Correction
4.3.4 Noise Filter
4.3.5 Pre Filter
为了减少LINE-CRAWLING，只针对green pixels.有两种方式（PRE_TYP选择）：1.常量 2.算法
4.3.6 White Balance
白平衡就是调整增益，有两种：
1.Digital gain调整影像总亮度，x 0 – x 3.996 (step = 1/256)
2. white balance gains 调整CFA中每个分量的增益，x 0 – x 7.992 (step = 1/128)
4.3.7 CFA Interpolation
由 Bayer RGB转换成RGB 4:4:4 data
4.3.8 RGB2RGB Blending（混合）
RGB混合，即增加一OFFSET，调成人类的色彩光谱。(RGB_MUL_[R,G,B][R,G,B], & RGB_OFT_[R,G,B])
4.3.9 Gamma Correction Module
摄像时亮度与电压成非线性关系，称此为GAMMA曲线，GAMMA校正即是校正此非线性
有三个通路：1.BYPASS 2. 从RAM TABLE 3. 从ROM TABLE
4.3.10 RGB2YCbCr Conversion Module
YCC_MUL_[R,G,B][Y,CB,CR], and YCC_OFT_[Y,CB,CR]
4.3.11 4:2:2 Conversion Module
转换成YCBCR422格式
4.3.12 2-D Edge Enhancer
针对亮度信号，提高IMAGE质量。YEE_EN.EN开启。用一高通FILER来获取图像边缘，FILER系数可编程(YEE_MUL_[0,1,2][0,1,2])，输出可下SHIFT（YEE_SHF.SHF）。增加RAM表值可加强sharpness
4.3.13 Median NR
用来减少边缘强度的pseudo peak（假峰值），YEE_EMF.EN开启
4.3.14 Chrominance Suppression
FCS_EN.EN开启。在图像的亮度很强区域，可能会有一两个色彩通道饱和，但其它色彩没有，这样就会造成假色彩，如最常出现的就是原本是白色的却出现的是粉红色， 色度抑制可减少假色彩。
4.3.15 Horizontal and Vertical Resize Module
范围： x1/16 scale-down to x8
参数：RSZ[n].RSZ_H_TYP类型选择，HRSZ (RSZ[n].RSZ_H_DIF) and VRSZ (RSZ[n].RSZ_V_DIF)比例，上下限为32-4096，对应X8-X1/16，实际以256/HRSZ，256/VRSZ计算，影像输出尺寸最大为1344 pixels/line for RSZ[0] and 640 pixels/line for RSZ[1].
Vertical resize有两种模式：输入行号模式（RSZ_SEQ.TMM = 1)，连续模式。RSZ[n].RSZ_V_PHS_O定义最后输出位置
4.3.16 Output Interface
YCC_Y_MAX, YCC_Y_MIN, YCC_C_MAX, and YCC_C_MIN 定义Y，C大小范围，YCBCR422 TO YCBCR444，TO RGB，输出32BIT
4.3.17 RGB Converter
在H/V RESIZER中，YCBCR422通过线性插值，转成YCBCR444，由于此关系，第一行的一前一后两个像素会丢失，即RESIZE后会比想要的少两个像素。
在SDRAM BURST（256BIT）时以数据打包方式访问，有两种打包方式，32BIT，16BIT，(RSZ[n].RGB_TYP.TYP选择。32BIT时输出RGB各8位，及8BIT alpha value(在RSZ[n].RGB_BLD设定）；In 16-bit mode, R (5-bit), G (6-bit), and B (5-bit)输入到SDRAM。
4.4 H3A
5 Programming Model
VPFE Memory Master Selection
Shared Memory Register Field Settings
Shared Read Buffer (SRB) PCR.RBLCTRL 0: IPIPEIF
1: Reserved
2: H3A
Shared Write Buffer (SWB) PCR.WBLCTRL 0: IPIPEIF
1: Reserved
DFC Table MEMCTRL.DFCCTRL 0: IPIPE
1: CCDC
RSZ Line Memory MEMCTRL.RSZ_CTRL 0: IPIPEIF
1: Reserved
5.4 编程CCDC
模块能动：SYNCEN.VDHDEN能动CCDC，在能动之前需先设置一些REG。
SYNCEN.WEN 写SDRAM能动
若CCDC为MASTER MODE，则当SYNCEN.VDHDEN 后立即进行数据处理
若CCDC为SLAVE MODE, 则 SYNCEN.VDHDEN 应先于外部设备打开,以免数据丢失
设置顺序:
1. Set Data output address (STADRH & STADRL).
2. Enable HD/VD and WEN at the same time (MODESET.WEN & SYNCEN.VDHDEN)
中断:
VDINT0, VDINT1, and VDINT2
VDINT0,VDINT1达到VDINT.VDINT0 and VDINT.VDINT1中的行数后中断
VDINT2 以 CAM_WEN_FIELD为参考,在下降沿中断
MODESET.FLDSTAT场状态指示
REG整体上可分两种：
Shadowed Registers (event latched registers)—可随时读写，但只有当一定的事件发生时才起作用
Busy-Writeable Registers—可随时读写，即时发生作用
5.5 Programming the Image Pipe Interface (IPIPEIF)
模块能动：ENABLE.ENABLE ，当输入为CCDC RAW时，不需能动，CCDC 送什么就处理什么
当输入为SDRAM时CFG.ONESHOT定义ONESHOT模式还是CONTINOUS模式。在ONESHOT模式，只有一FRAME被处理，且ENABLE.ENABLE自动清0
会产生一 IPIPEIF event to the VPSSBL
5.6 Programming the Image Pipe (IPIPE)
模块能动：IPIPE_EN.EN
IPIPE EVENT
IRQ0 Final pixel from each frame is flushed from the image pipe (not resizer) and histogram completion event
IRQ1 SDRAM Write Completion Event
IRQ2 RZA Interval Completion Event
IRQ3 RZB Interval Completion Event
IRQ5 Register Update Ready Notification Event
5.6.1.2.1 Resizer Bypass Mode
Since the YCbCr data still passes through the RZA block in resizer bypass mode, the following registers
must be set accordingly:
GCK_SDR = 0 RSZ[0].RSZ_V_DIF = 256
RSZ_SEQ.SEQ = 0 RSZ[0].RSZ_H_PHS = 0
RSZ_SEQ.TMM = 0 RSZ[0].RSZ_H_DIF = 256
RSZ_AAL = 0 RSZ[0].RSZ_H_LSE = 0
RSZ[0].RSZ_O_HPS = 0 RSZ[1].RSZ_EN = 0
RSZ[0].RSZ_V_PHS = 0
5.6.1.2.2 RAW input, RAW output Mode (IPIPE_DPATHS.FMT = 1)
In this mode, the RAW data bypasses the RAW to YCbCr processes (see Figure 37), but since it still
passes through the YCbCr processing blocks, the following registers must be set accordingly:
IPIPE_DPATHS.FMT = 1 YEE_EN = 0 RSZ[0].RSZ_V_DIF = 256
BOX_EN = 0 FCS_EN = 0 RSZ[0].RSZ_H_PHS = 0
YCC_ADJ.CTR = 16 RSZ_SEQ.TMM = 0 RSZ[0].RSZ_H_DIF = 256
YCC_ADJ.BRT = 0 RSZ[0].RSZ_EN = 1 RSZ[0].RSZ_H_TYP = 0
YCC_Y_MIN = 0 RSZ[0].RSZ_I_VPS = 0 RSZ[0].RSZ_H_LSE = 0
YCC_Y_MAX = 255 RSZ[0].RSZ_I_HPS = 0 RSZ[0].RSZ_H_LPF = 0
YCC_C_MIN = 0 RSZ[0].RSZ_O_HPS = 0 RSZ[0].RSZ_RGB_EN = 0
YCC_C_MAX = 255 RSZ[0].RSZ_V_PHS = 0 RSZ[1].RSZ_EN = 0
5.6.1.3.1 Read/Write Procedures
The IPIPE internal memory values can be written, read, and written after read. If multiple values need to
be set in incremental addresses, then the RAM_MODE.ADR bit can be set so that only the first address
needs to be set and subsequent reads/writes will auto-increment the internal address. The following
procedures should be followed to access the internal memories:
For memory write:
1. Write to RAM_MODE: set memory selection and set EXT = 0 andWDT = 1.
2. Write to RAM_ADR: set starting offset into memory.
3. Write to RAM_WDT: Write data.
For memory read:
1. Write to RAM_MODE: set memory selection and set EXT = 0 andWDT = 0.
2. Write to RAM_ADR: set starting offset into memory.
3. Write to RAM_WDT: Write dummy data.
4. Read the data of the internal memory from RAM_RDT.
For memory write after read:
1. Write to RAM_MODE: set memory selection and set EXT = 0 andWDT = 1.
2. Write to RAM_ADR: set starting offset into memory.
3. Write to RAM_WDT: Write data.
4. Read the data of the internal memory from RAM_RDT.
5.7 Programming the Hardware 3A (H3A)
模块能动： PCR.AF_EN ，PCR.AEW_EN
当输入为SDRAM时，ONE-SHOT模式处理.若要处理每FRAME,则需设定PCR.SDR_FETCH_EN
当输入为CCDC时, CONTINUOUS模式处理,此时依据CCDC的时序来处理.应先CCDC能动
此模块处理完一FRAME后,可产生一中断和一EVENT
5.8 Programming the Buffer Logic (VPSSBL and VPSSCLK Registers)
VPSSBL and VPSSCLK Required Configuration Parameters
Function Configuration Required
CCDC VPSSBL.MEMCTRL.DFCCTRL
VPSSCLK.CLKCTRL.CCDCCLK
IPIPEIF VPSSBL.PCR.RBLCTRL
VPSSCLK.CLKCTRL.IPIPECLK
IPIPE VPSSBL.PCR.WBLCTRL
VPSSBL.MEMCTRL.IPIPE_WD_EN
VPSSBL.MEMCTRL.RESZ_CTRL
VPSSBL.MEMCTRL.DFCCTRL
VPSSCLK.CLKCTRL.IPIPECLK
H3A VPSSBL.PCR.RBLCTRL
VPSSCLK.CLKCTRL.H3ACLK
中断及事件选择VPSSBL.INTSEL and VPSSBL.EVTSEL
1.OVERVIEW
1.1 CCDC
1）产生SD，HD时序信号
2）可编程镜头阴影校正（ Lens Shading Correction）.
3）支持BT656，YCBCR422（8BIT，16BIT，WITH HS，VS），及14BIT RAW DATA FROM CCD/CMOS
4) 可编程14BIT 到8BIT输出
5）可通过外部写能动信号EN控制向DDR写数据
6）SENSOR CLK可达75MHZ，若用到H3A，则只能达67.5MHZ
7）DEFECT CORRECT
1.2.H3A
1）auto white balance and auto eexposure by collecting metrics（统计）
2）读写DDR
3）只接收RAW DATA
1.3.IPIPE
1）只接收RAW DATA ，且转换14BIT RAW DATA为YCBCR422或YCRCR422 RESIZE
2）支持RGB Bayer pattern，经过彩色空间转换也支持CMYG
3）每个分量增益控制
4）可编程的RGB TO YCBCR的转换系数
5）可配置成仅RESIZE模式，即直接YCBCR422 RESIZE，不经过其它模块处理
6）RGB (32bit/16bit) output to SDRAM
7）要求至少BLANK 8PIXEL/行，4行 BLANK，在ONE SHOT 下，至少10行 BLANK，在处理之后
8）最大支持1344PIXEL 输入输出宽度
9）DEFECT CORRECT
1.4.IPIPEIF
1）读CCDC，SDRAM，写IPIPE
2）重新调整 HD, VD, and PCLK timing to the IPIPE input.
3）dark-frame subtract黑色帧消除法降噪（用于长时间瀑光引起的噪声点）
2.引脚IO 接口
1. YIN[7..0]/CCDIN[7..0]
2. CIN[5..0]/CCDIN[13..0]
3.PCLK
4.CAM_HD,CAM_VD
5.CAM_WEN_FIELD:/设 CCD Write Enable/Field ID signal
1）作FIELD标识信号，FLDMODE定类型提供，由CCD/CMOSFIDMD/FLDPOL
2）作WEN用，EXWEN打开，WENLOG设定AND 或 OR，与在SPH, NPH, SLV, NLV内的有效像素相AND或OR
RAM模式引脚:
以上全需用到
另少于14BIT时,一般用CCD[13..0]高位,舍去底位,当用时SPI时除外
----------------------------------------------------------------
引脚配置REG: PINMUX0(VPFE.PDF PAGE38)
3。VPFE/ISP Integration
VPSS Events:9个作为中断送ARM，4个作为EVENT送EDMA
Number Acronym Module Description
0 CCDC VDINT0 CCDC Triggered after a programmable number of input lines for each frame.
1 CCDC VDINT1 CCDC Triggered after a programmable number of input lines for each frame.
2 CCDC VDINT2 CCDC Triggered at the rising edge of WEN signal
3 H3AINT H3A Triggered at the end of AF or AEW writes to DDR for each frame
4 VENCINT VENC Triggered at the rising edge of VSYNC
5 OSDINT OSD Triggered at the end of each frame read from DDR
6 IPIPEIFINT IPIPEIF Triggered at the rising edge of VD if enabled
7 IPIPE_INT0_HST IPIPE Triggered when Histogram processing is finished for each frame
8 IPIPE_INT1_SDR IPIPE Triggered when writes to DDR are finished for each frame
9 IPIPE_INT2_RZA IPIPE Triggered when the number of lines programmed has been output of RZA
10 IPIPE_INT3_RZB IPIPE Triggered when the number of lines programmed has been output of RZB
12 IPIPE_INT5_MMR IPIPE Triggered when MMR modifications for the next frame can be made
中断：VPSSBL.INTSEL选择
INT Number Acronym
0 VPSSINT0
1 VPSSINT1
2 VPSSINT2
3 VPSSINT3
4 VPSSINT4
5 VPSSINT5
6 VPSSINT6
7 VPSSINT7
8 VPSSINT8
事件：VPSSBL.EVTSEL选择
Event Number Binary Event Name
4 0000100 VPSSEVT1
5 0000101 VPSSEVT2
6 0000110 VPSSEVT3
7 0000111 VPSSEVT4
VPSS REG：
VPFE Module Register Map
VPSS Registers Address Range Size
VPSSCLK 0x01C70000 0x01C7007F 128B
H3A 0x01C70080 0x01C700FF 128B
IPIPEIF 0x01C70100 0x01C701FF 256B
OSD 0x01C70200 0x01C702FF 256B
VENC 0x01C70400 0x01C705FF 512B
CCDC 0x01C70600 0x01C707FF 512B
VPSSBL 0x01C70800 0x01C708FF 256B
IPIPE 0x01C71000 0x01C73FFF 12K-
-------------------------------------------------------------------------
4 。VPFE/ISP Functional Description
4.1 CCDC
参数：MODESET.INPMOD输出到DDR的数据选择，YCBCR或RGB
RAW模式时序参数：HDW，VDW，PPLN，HLPFR （从AFE来）
RAW模式时CCDCFG.YCINSWP=0
4.1.2.1 DIGITAL CLAMP
CLAMP的黑电平可用常量也可从像素中计算得到,也可从CCD SENSOR的上黑边，左黑边提取基量
以求平均值计算。
参数：CLAMP.OBST 黑像素开始点；CLAMP.OBSLEN每行的用来求平均的像素数；DCSUB.OBSLN求平均的行数
4.1.2.2 Color Space Conversion
CSCCTL[0]开启。由乘加器，LINE MEMORY组成，CMYG--》RGBG
FMTSPH, FMTLNH, FMTSLV, and FMTLNV指定数据区域
转换后数据会有一行LATENCY（延迟）。
最后一行至少要有一无效像素，一FRAME中至少要有一无效行
4.1.2.3 Defect Correction：坏点校正
DFCCTL[0]开启，可校正1024个点
4.1.2.4 Lens Shading Correction：镜头阴影校正
LSCCFG[0]开启，由于镜头中心较亮，向边缘渐暗。由此而校正
4.1.2.5 Black Level Compensation：太亮，太暗补偿
BLKCMP0.R_YE, BLKCMP0.GR_CY, BLKCMP1.GB_G, BLKCMP1.B_MG)
4.1.2.6 Median Filter：中央滤波。一路送SDRAM，另一路送IPIPE，可单独能动
1. Average Filter Configuration
2. Median Filter Configuration
GAMMAWD.MFILT1 and GAMMAWD.MFILT2
4.1.2.7 SDRAM RAW Output Formatting
4.1.4 Data Output Control
• SDOFST.FIINV – invert interpretation of the Field ID signal
• SDOFST.FIINV – invert interpretation of the Field ID signal
• SDOFST.LOFTS0 – offset, in lines, between even lines on even fields (field 0)
• SDOFST.LOFTS1 – offset, in lines, between odd lines on even fields (field 0)
• SDOFST.LOFTS2 – offset, in lines, between even lines on odd fields (field 1)
• SDOFST.LOFTS3 – offset, in lines, between odd lines on odd fields (field 1)
4.2 IPIPEIF
参数：HDW=8PIXEL，VDW=4LINE（CONTINUE）OR 10LINE（ONE SHOT），PPLN=HD 间隔，LPFR=VD 间隔>1 LINE，HNUM=水平有效像素（从HD上升沿开始？？？），VNUM=垂直有效像素（从VD下降沿开始，即隔4或10LINE）
4.2.1.1 CCDC RAW Input Mode (CFG.INPSRC = 0)
14BIT
4.2.1.2 SDRAM RAW Input Mode (CFG.INPSRC = 1h)
从SDRAM中读取8BIT或16BIT，8BIT为经过A-LAW压缩的，可设CFG.IALAW解压，也可填0补齐
4.2.1.3 CCDC RAW Input With Dark Frame Subtract From SDRAM Mode (CFG.INPSRC = 2h)
IPIPEIF INPUT = CCDC RAW INPUT - SDRAM INPUT
此时PPLN，LPFR的意义与其它输入模式不同，表示从CCDC DATA中减去时的水平，垂直方向的起始位置
4.2.1.4 SDRAM YCbCr 4:2:2 Input Mode (CFG.INPSRC = 3h)
16BIT YCbCr 4:2:2 data
4.2.2 时序产生
当输入为0或2时，HD/VD/WEN ，PCLK由CCDC提供， 为1或3时，IPIEIF产生HD/VD（基于LPFR and PPLN），PCLK可继续用CCDC的PCLK（CFG.CLKSEL=0），也可自已产生（CFG.CLKSEL=1）（用VPSSCLK分频CFG.CLKDIV），产生PCLK时要考虑下面IPIPE RESIZE时最大时钟要求及SDRAM实时操作要求
当CFG.INPSRC非0时，IPIPE I/F SDRAM data读及时序产生即可在ONE-SHOT 下，也可在CONTINUE模式下（(ENABLE.ENABLE）
当输入大于1344PIXEL时开启CFG.DECM设定比例系数以缩小到1344以下
4.3 IPIPE
参数：IPIPE_HST,IPIPE_VST定义开始点（与HD，VD上升沿为原点），IPIPE_HSZ, IPIPE_VSZ定义要处理的数据区域大小
IPIPE_COLPAT定义处理数据的Color pattern
Input Modes (IPIPE_DPATHS.FMT)
0: RAW to YCbCr
1: RAW to RAW
2: RAW to Boxcar
3: YCbCr to YCbCr
In RAW pass through mode,可以支持最大4096PIXEL/LINE，直接写到SDRAM
4.3.3 Defect Correction
4.3.4 Noise Filter
4.3.5 Pre Filter
为了减少LINE-CRAWLING，只针对green pixels.有两种方式（PRE_TYP选择）：1.常量 2.算法
4.3.6 White Balance
白平衡就是调整增益，有两种：
1.Digital gain调整影像总亮度，x 0 – x 3.996 (step = 1/256)
2. white balance gains 调整CFA中每个分量的增益，x 0 – x 7.992 (step = 1/128)
4.3.7 CFA Interpolation
由 Bayer RGB转换成RGB 4:4:4 data
4.3.8 RGB2RGB Blending（混合）
RGB混合，即增加一OFFSET，调成人类的色彩光谱。(RGB_MUL_[R,G,B][R,G,B], & RGB_OFT_[R,G,B])
4.3.9 Gamma Correction Module
摄像时亮度与电压成非线性关系，称此为GAMMA曲线，GAMMA校正即是校正此非线性
有三个通路：1.BYPASS 2. 从RAM TABLE 3. 从ROM TABLE
4.3.10 RGB2YCbCr Conversion Module
YCC_MUL_[R,G,B][Y,CB,CR], and YCC_OFT_[Y,CB,CR]
4.3.11 4:2:2 Conversion Module
转换成YCBCR422格式
4.3.12 2-D Edge Enhancer
针对亮度信号，提高IMAGE质量。YEE_EN.EN开启。用一高通FILER来获取图像边缘，FILER系数可编程(YEE_MUL_[0,1,2][0,1,2])，输出可下SHIFT（YEE_SHF.SHF）。增加RAM表值可加强sharpness
4.3.13 Median NR
用来减少边缘强度的pseudo peak（假峰值），YEE_EMF.EN开启
4.3.14 Chrominance Suppression
FCS_EN.EN开启。在图像的亮度很强区域，可能会有一两个色彩通道饱和，但其它色彩没有，这样就会造成假色彩，如最常出现的就是原本是白色的却出现的是粉红色， 色度抑制可减少假色彩。
4.3.15 Horizontal and Vertical Resize Module
范围： x1/16 scale-down to x8
参数：RSZ[n].RSZ_H_TYP类型选择，HRSZ (RSZ[n].RSZ_H_DIF) and VRSZ (RSZ[n].RSZ_V_DIF)比例，上下限为32-4096，对应X8-X1/16，实际以256/HRSZ，256/VRSZ计算，影像输出尺寸最大为1344 pixels/line for RSZ[0] and 640 pixels/line for RSZ[1].
Vertical resize有两种模式：输入行号模式（RSZ_SEQ.TMM = 1)，连续模式。RSZ[n].RSZ_V_PHS_O定义最后输出位置
4.3.16 Output Interface
YCC_Y_MAX, YCC_Y_MIN, YCC_C_MAX, and YCC_C_MIN 定义Y，C大小范围，YCBCR422 TO YCBCR444，TO RGB，输出32BIT
4.3.17 RGB Converter
在H/V RESIZER中，YCBCR422通过线性插值，转成YCBCR444，由于此关系，第一行的一前一后两个像素会丢失，即RESIZE后会比想要的少两个像素。
在SDRAM BURST（256BIT）时以数据打包方式访问，有两种打包方式，32BIT，16BIT，(RSZ[n].RGB_TYP.TYP选择。32BIT时输出RGB各8位，及8BIT alpha value(在RSZ[n].RGB_BLD设定）；In 16-bit mode, R (5-bit), G (6-bit), and B (5-bit)输入到SDRAM。
4.4 H3A
5 Programming Model
VPFE Memory Master Selection
Shared Memory Register Field Settings
Shared Read Buffer (SRB) PCR.RBLCTRL 0: IPIPEIF
1: Reserved
2: H3A
Shared Write Buffer (SWB) PCR.WBLCTRL 0: IPIPEIF
1: Reserved
DFC Table MEMCTRL.DFCCTRL 0: IPIPE
1: CCDC
RSZ Line Memory MEMCTRL.RSZ_CTRL 0: IPIPEIF
1: Reserved
5.4 编程CCDC
模块能动：SYNCEN.VDHDEN能动CCDC，在能动之前需先设置一些REG。
SYNCEN.WEN 写SDRAM能动
若CCDC为MASTER MODE，则当SYNCEN.VDHDEN 后立即进行数据处理
若CCDC为SLAVE MODE, 则 SYNCEN.VDHDEN 应先于外部设备打开,以免数据丢失
设置顺序:
1. Set Data output address (STADRH & STADRL).
2. Enable HD/VD and WEN at the same time (MODESET.WEN & SYNCEN.VDHDEN)
中断:
VDINT0, VDINT1, and VDINT2
VDINT0,VDINT1达到VDINT.VDINT0 and VDINT.VDINT1中的行数后中断
VDINT2 以 CAM_WEN_FIELD为参考,在下降沿中断
MODESET.FLDSTAT场状态指示
REG整体上可分两种：
Shadowed Registers (event latched registers)—可随时读写，但只有当一定的事件发生时才起作用
Busy-Writeable Registers—可随时读写，即时发生作用
5.5 Programming the Image Pipe Interface (IPIPEIF)
模块能动：ENABLE.ENABLE ，当输入为CCDC RAW时，不需能动，CCDC 送什么就处理什么
当输入为SDRAM时CFG.ONESHOT定义ONESHOT模式还是CONTINOUS模式。在ONESHOT模式，只有一FRAME被处理，且ENABLE.ENABLE自动清0
会产生一 IPIPEIF event to the VPSSBL
5.6 Programming the Image Pipe (IPIPE)
模块能动：IPIPE_EN.EN
IPIPE EVENT
IRQ0 Final pixel from each frame is flushed from the image pipe (not resizer) and histogram completion event
IRQ1 SDRAM Write Completion Event
IRQ2 RZA Interval Completion Event
IRQ3 RZB Interval Completion Event
IRQ5 Register Update Ready Notification Event
5.6.1.2.1 Resizer Bypass Mode
Since the YCbCr data still passes through the RZA block in resizer bypass mode, the following registers
must be set accordingly:
GCK_SDR = 0 RSZ[0].RSZ_V_DIF = 256
RSZ_SEQ.SEQ = 0 RSZ[0].RSZ_H_PHS = 0
RSZ_SEQ.TMM = 0 RSZ[0].RSZ_H_DIF = 256
RSZ_AAL = 0 RSZ[0].RSZ_H_LSE = 0
RSZ[0].RSZ_O_HPS = 0 RSZ[1].RSZ_EN = 0
RSZ[0].RSZ_V_PHS = 0
5.6.1.2.2 RAW input, RAW output Mode (IPIPE_DPATHS.FMT = 1)
In this mode, the RAW data bypasses the RAW to YCbCr processes (see Figure 37), but since it still
passes through the YCbCr processing blocks, the following registers must be set accordingly:
IPIPE_DPATHS.FMT = 1 YEE_EN = 0 RSZ[0].RSZ_V_DIF = 256
BOX_EN = 0 FCS_EN = 0 RSZ[0].RSZ_H_PHS = 0
YCC_ADJ.CTR = 16 RSZ_SEQ.TMM = 0 RSZ[0].RSZ_H_DIF = 256
YCC_ADJ.BRT = 0 RSZ[0].RSZ_EN = 1 RSZ[0].RSZ_H_TYP = 0
YCC_Y_MIN = 0 RSZ[0].RSZ_I_VPS = 0 RSZ[0].RSZ_H_LSE = 0
YCC_Y_MAX = 255 RSZ[0].RSZ_I_HPS = 0 RSZ[0].RSZ_H_LPF = 0
YCC_C_MIN = 0 RSZ[0].RSZ_O_HPS = 0 RSZ[0].RSZ_RGB_EN = 0
YCC_C_MAX = 255 RSZ[0].RSZ_V_PHS = 0 RSZ[1].RSZ_EN = 0
5.6.1.3.1 Read/Write Procedures
The IPIPE internal memory values can be written, read, and written after read. If multiple values need to
be set in incremental addresses, then the RAM_MODE.ADR bit can be set so that only the first address
needs to be set and subsequent reads/writes will auto-increment the internal address. The following
procedures should be followed to access the internal memories:
For memory write:
1. Write to RAM_MODE: set memory selection and set EXT = 0 andWDT = 1.
2. Write to RAM_ADR: set starting offset into memory.
3. Write to RAM_WDT: Write data.
For memory read:
1. Write to RAM_MODE: set memory selection and set EXT = 0 andWDT = 0.
2. Write to RAM_ADR: set starting offset into memory.
3. Write to RAM_WDT: Write dummy data.
4. Read the data of the internal memory from RAM_RDT.
For memory write after read:
1. Write to RAM_MODE: set memory selection and set EXT = 0 andWDT = 1.
2. Write to RAM_ADR: set starting offset into memory.
3. Write to RAM_WDT: Write data.
4. Read the data of the internal memory from RAM_RDT.
5.7 Programming the Hardware 3A (H3A)
模块能动： PCR.AF_EN ，PCR.AEW_EN
当输入为SDRAM时，ONE-SHOT模式处理.若要处理每FRAME,则需设定PCR.SDR_FETCH_EN
当输入为CCDC时, CONTINUOUS模式处理,此时依据CCDC的时序来处理.应先CCDC能动
此模块处理完一FRAME后,可产生一中断和一EVENT
5.8 Programming the Buffer Logic (VPSSBL and VPSSCLK Registers)
VPSSBL and VPSSCLK Required Configuration Parameters
Function Configuration Required
CCDC VPSSBL.MEMCTRL.DFCCTRL
VPSSCLK.CLKCTRL.CCDCCLK
IPIPEIF VPSSBL.PCR.RBLCTRL
VPSSCLK.CLKCTRL.IPIPECLK
IPIPE VPSSBL.PCR.WBLCTRL
VPSSBL.MEMCTRL.IPIPE_WD_EN
VPSSBL.MEMCTRL.RESZ_CTRL
VPSSBL.MEMCTRL.DFCCTRL
VPSSCLK.CLKCTRL.IPIPECLK
H3A VPSSBL.PCR.RBLCTRL
VPSSCLK.CLKCTRL.H3ACLK
中断及事件选择VPSSBL.INTSEL and VPSSBL.EVTSEL
DM355 Reset Types
Type Initiator Effect
POR (Power-On-Reset) RESETN pin low and TRSTN low Total reset of the chip (cold reset). Resets all modules including memory and emulation.
Warm Reset RESETN pin low and TRSTN high (initiated by Resets all modules including memory, except ARM
ARM emulator). emulation.
Max Reset ARM emulator or Watchdog Timer (WDT). Same effect as warm reset.
System Reset ARM emulator Resets all modules except memory and ARM
emulation. It is a soft reset that maintains memory contents and does not affect or reset clocks or power states.
Module Reset ARM software Resets a specific module. Allows the ARM software
to independently reset a module. Module reset is intended as a debug tool not as a tool to use in production.
POR (Power-On-Reset) RESETN pin low and TRSTN low Total reset of the chip (cold reset). Resets all modules including memory and emulation.
Warm Reset RESETN pin low and TRSTN high (initiated by Resets all modules including memory, except ARM
ARM emulator). emulation.
Max Reset ARM emulator or Watchdog Timer (WDT). Same effect as warm reset.
System Reset ARM emulator Resets all modules except memory and ARM
emulation. It is a soft reset that maintains memory contents and does not affect or reset clocks or power states.
Module Reset ARM software Resets a specific module. Allows the ARM software
to independently reset a module. Module reset is intended as a debug tool not as a tool to use in production.
DM355 MEMORY MAPPING
4.Memory Mapping
4.1 Memory Map
Table 4-1. DM355 Memory Map
Start Address End Address Size (Bytes) ARM
EDMA USB VPSS
Mem Map Mem Map
Mem Map Mem Map
0x0000 0000 0x0000 3FFF 16K ARM RAM0
(Instruction)
----------------------------------------------------------------------------------------------
0x0000 0000 0x00007FFF 16K ARMRAM1 Reserved
Reserved
(Instruction)
----------------------------------------------------------------------------------------------
0x0000 8000 0x0000 FFFF 32K ARM ROM
(Instruction)
- only 8K used
----------------------------------------------------------------------------------------------
0x0001 0000 0x0001 3FFF 16K ARM RAM0 (Data) ARM
RAM0 ARM RAM0
----------------------------------------------------------------------------------------------
0x0001 4000 0x0001 7FFF 16K ARM RAM1 (Data) ARM
RAM1 ARM RAM1
----------------------------------------------------------------------------------------------
0x0001 8000 0x0001 FFFF 32K ARM ROM (Data) ARM
ROM ARM ROM
- only 8K used
----------------------------------------------------------------------------------------------
0x0002 0000 0x000F FFFF 896K Reserved
----------------------------------------------------------------------------------------------
0x0010 0000 0x01BB FFFF 26M
----------------------------------------------------------------------------------------------
0x01BC 0000 0x01BC 0FFF 4K ARM ETB Mem
----------------------------------------------------------------------------------------------
0x01BC 1000 0x01BC 17FF 2K ARM ETB Reg Reserved
----------------------------------------------------------------------------------------------
0x01BC 1800 0x01BC 18FF 256 ARM IceCrusher Reserved
----------------------------------------------------------------------------------------------
0x01BC 1900 0x01BC FFFF 59136 Reserved
----------------------------------------------------------------------------------------------
0x01BD 0000 0x01BF FFFF 192K
----------------------------------------------------------------------------------------------
0x01C0 0000 0x01FF FFFF 4M CFGBus CFG
Bus Reserved
Peripherals Peripherals
----------------------------------------------------------------------------------------------
0x0200 0000 0x09FF FFFF 128M ASYNC EMIF ASYNC EMIF
(Data) (Data)
----------------------------------------------------------------------------------------------
0x0A00 0000 0x11EF FFFF 127M - 16K
----------------------------------------------------------------------------------------------
0x11F0 0000 0x11F1 FFFF 128K Reserved Reserved
----------------------------------------------------------------------------------------------
0x11F2 0000 0x1FFF FFFF 141M-64K
----------------------------------------------------------------------------------------------
0x2000 0000 0x2000 7FFF 32K DDR EMIF Control DDR EMIF
Control
Regs Regs
----------------------------------------------------------------------------------------------
0x2000 8000 0x41FF FFFF 544M-32K Reserved
----------------------------------------------------------------------------------------------
0x4200 0000 0x49FF FFFF 128M Reserved AEMIF -
shadow
----------------------------------------------------------------------------------------------
0x4A00 0000 0x7FFF FFFF 864M Reserved
----------------------------------------------------------------------------------------------
0x8000 0000 0x8FFF FFFF 256M DDR EMIF DDR EMIF
DDR EMIF DDR EMIF
----------------------------------------------------------------------------------------------
0x9000 0000 0xFFFF FFFF 1792M Reserved Reserved
Reserved Reserved
4.1.1 ARM Internal Memories
32KB ARM Internal RAM（与TCM接口）可分成2PAGE
8KB ARM Internal ROM
注：ARM access to internal memory is with one wait-state.当ARM
频率少于或等于150M时可设置zero wait-state，用Miscellaneous Control
register (MISC）之AIM_WAIST来设置
4.1.2 External Memories
· DDR2 / mDDR Synchronous DRAM
· Asynchronous EMIF/OneNand
· NAND Flash
· External Host Devices
此外还可访问各种多媒存储接口
4.1.3 MPEG/JPEG Coprocessor (MJCP)
4.1.4 Peripherals
ARM和EDMA可访问以下外部设备
· EDMA Controller
· Three UARTs
· I2C (Inter-IC Communication)
· Three 64-bit timers (each configurable as one 64-bit timer or two 32 bit
timers) and one WDT
· PWM (Pulse Width Modulator)
· USB (Universal Serial Bus Controller)
· Three SPI serial interfaces
· General-Purpose Input/Output (GPIO)
· Video Processing Subsystem (VPSS)
· Asynchronous EMIF (AEMIF) Controller
· Real Time Out (RTO)
也可访问以下内部设置
· ETM/ETB
· ICEcrusher
· System Module
· PLL Controllers
· Power Sleep Controller
· ARM Interrupt Controller
DM355 ARM Configuration Bus Access to Peripherals
Address
Accessibility
Region Start End
Size ARM EDMA
EDMA CC 0x01C0 0000 0x01C0 FFFF 64K
EDMA TC0 0x01C1 0000 0x01C1 03FF 1K
EDMA TC1 0x01C1 0400 0x01C1 07FF 1K
Reserved 0x01C1 8800 0x01C1 9FFF 6K
Reserved 0x01C1 A000 0x01C1 FFFF 24K
UART0 0x01C2 0000 0x01C2 03FF 1K
UART1 0x01C2 0400 0x01C2 07FF 1K
Timer4/5 0x01C2 0800 0x01C2 0BFF 1K
Real-time out 0x01C2 0C00 0x01C2 0FFF 1K
I2C 0x01C2 1000 0x01C2 13FF 1K
Timer0/1 0x01C2 1400 0x01C2 17FF 1K
Timer2/3 0x01C2 1800 0x01C2 1BFF 1K
WatchDog Timer 0x01C2 1C00 0x01C2 1FFF 1K
PWM0 0x01C2 2000 0x01C2 23FF 1K
PWM1 0x01C2 2400 0x01C2 27FF 1K
PWM2 0x01C2 2800 0x01C2 2BFF 1K
PWM3 0x01C2 2C00 0x01C2 2FFF 1K
System Module 0x01C4 0000 0x01C4 07FF 2K
PLL Controller 0 0x01C4 0800 0x01C4 0BFF 1K
PLL Controller 1 0x01C4 0C00 0x01C4 0FFF 1K
Power/Sleep Controller 0x01C4 1000 0x01C4 1FFF 4K
ARM Interrupt Controller 0x01C4 8000 0x01C4 83FF 1K
USB OTG 2.0 Regs / RAM 0x01C6 4000 0x01C6 5FFF 8K
SPI0 0x01C6 6000 0x01C6 67FF 2K
SPI1 0x01C6 6800 0x01C6 6FFF 2K
GPIO 0x01C6 7000 0x01C6 77FF 2K
SPI2 0x01C6 7800 0x01C6 FFFF 2K
VPSS Subsystem 0x01C7 0000 0x01C7 FFFF 64K
VPSS Clock Control 0x01C7 0000 0x01C7 007F 128
Hardware 3A 0x01C7 0080 0x01C7 00FF 128
Image Pipe (IPIPE) 0x01C7 0100 0x01C7 01FF 256
Interface
On Screen Display 0x01C7 0200 0x01C7 02FF 256
High Speed Serial IF 0x01C7 0300 0x01C7 03FF 256
Video Encoder 0x01C7 0400 0x01C7 05FF 512
CCD Controller 0x01C7 0600 0x01C7 07FF 256
VPSS Buffer Logic 0x01C7 0800 0x01C7 08FF 256
CFA Multiply Mask / Lens 0x01C7 0900 0x01C7 09FF 256
Distortion
Image Pipe (IPIPE) 0x01C7 1000 0x01C7 3FFF 12K
Reserved 0x01CC 0000 0x01CD FFFF 128K
Reserved 0x01CD 0000 0x01CD 007F 128
Reserved 0x01CD 0380 0x01CD 03FF 128
Reserved 0x01CD F400 0x01CD F4FF 256
Sequencer 0x01CD FF00 0x01CD FFFF 256
Multimedia / SD 1 0x01E0 0000 0x01E0 1FFF 8K
ASP0 0x01E0 2000 0x01E0 3FFF 8K
ASP1 0x01E0 4000 0x01E0 5FFF 8K
UART2 0x01E0 6000 0x01E0 63FF 1K
Reserved 0x01E0 6400 0x01E0 FFFF 39K
ASYNC EMIF Control 0x01E1 0000 0x01E1 0FFF 4K
Multimedia / SD 0 0x01E1 1000 0x01E1 FFFF 60K
Reserved 0x01E2 0000 0x01FF FFFF 1792K
ASYNC EMIF Data (CE0) 0x0200 0000 0x03FF FFFF 32M
ASYNC EMIF Data (CE1) 0x0400 0000 0x05FF FFFF 32M
Reserved 0x0A00 0000 0x0BFF FFFF 32M
Reserved 0x0C00 0000 0x0FFF FFFF 64M
4.2 Memory Interfaces Overview
4.2.1 DDR2 EMIF 只支持16位BUS
· Buffering input image data from sensors or video sources,
· Intermediate buffering for processing/resizing of image data in the VPFE,
· Numerous OSD display buffers
· Intermediate buffering for large raw Bayer data image files while
performing still camera processing
functions
· Buffering for intermediate data while performing video encode and decode
functions
· Storage of executable firmware for the ARM
· etc.
4.2.2 External Memory Interface
· Asynchronous memories (SRAM, Linear flash, etc.)
· NAND flash memories
· OneNAND flash memories
4.2.2.1 Asynchronous EMIF (AEMIF)
· SRAM on up to two asynchronous chip selects
· Supports 8-bit or 16-bit data bus widths
· Programmable asynchronous cycle timings
· Supports extended waits
· Supports Select Strobe mode
· Supports booting DM355's ARM processor from CE0 (e.g SRAM) via direct
execution
SPRUFB3–
4.2.2.2 NAND (NAND, SmartMedia, xD)
The NAND mode supports the following features:
· NAND Flash on up to two asynchronous chip selects
· Supports 8-bit and 16-bit data bus widths
· Programmable cycle timings
· Performs 1-bit and 4-bit ECC calculation (does not perform error
correction)
· NAND Mode also supports SmartMedia/SSFDC (Solid State Floppy Disk
Controller) and xD memory
cards
· ARM ROM supports booting of DM355's ARM processor from NAND-Flash
located at CE0
4.2.2.3 OneNAND
The OneNAND mode supports the following features:
· OneNAND Flash on up to two chip selects
· Supports only 16-bit data bus widths
· Supports asynchronous writes and reads
· Supports synchronous reads with continuous linear burst mode
· Does not support synchronous reads with wrap burst modes
· Programmable cycle timings for each chip select in asynchronous mode
· Supports booting of DM355's ARM processor from OneNAND-Flash located at
CE0 via direct
execution
34
5.1 Overview
5.2 Peripheral Clocking Considerations
5.2.1 Video Processing Back End Clocking
VPBE时钟分内部外部，内部用PLL1 之SYSCLK4
外部用：
· 24 MHz crystal input at MXI1
· 27 MHz crystal input at MXI2 (optional feature)
· PLL1 SYSCLK3
· EXTCLK pin (external VPBE clock input pin)
· PCLK pin (VPFE pixel clock input pin)
。。。。。。。。
6.6 PLL Controller Register Map
7.Power and Sleep Controller
Table 7-1. Module Configuration
Default States
Module Module Name Power Domain Power Domain State Module State
Number
0 VPSS Master AlwaysOn ON SyncRst
1 VPSS Slave AlwaysOn ON SyncRst
2 EDMA (CC) AlwaysOn ON BTSEL[1:0] = 00 – Enable (NAND)
BTSEL[1:0] = 01 – Enable (OneNAND)
3 EDMA (TC0) AlwaysOn ON BTSEL[1:0] = 10 – SyncRst (MMC/SD)
BTSEL[1:0] = 11 – Enable (UART)
4 EDMA (TC1) AlwaysOn ON SyncRst
5 TIMER3 AlwaysOn ON SyncRst
6 SPI1 AlwaysOn ON SyncRst
7 MMC/SD1 AlwaysOn ON SyncRst
8 ASP1 AlwaysOn ON SyncRst
9 USB AlwaysOn ON SyncRst
10 PWM3 AlwaysOn ON SyncRst
11 SPI2 AlwaysOn ON SyncRst
12 RTO AlwaysOn ON SyncRst
13 DDR EMIF AlwaysOn ON SyncRst
14 AEMIF AlwaysOn ON BTSEL[1:0] = 00 – Enable (NAND)
BTSEL[1:0] = 01 – Enable (OneNAND)
BTSEL[1:0] = 10 – SyncRst (MMC/SD)
BTSEL[1:0] = 11 – Enable (UART)
15 MMC/SD0 AlwaysOn ON BTSEL[1:0] = 00 – SyncRst (NAND)
BTSEL[1:0] = 01 – SyncRst (OneNAND)
BTSEL[1:0] = 10 – Enable (MMC/SD)
BTSEL[1:0] = 11 – SyncRst (UART)
16 MemStick AlwaysOn ON SyncRst
17 ASP0 AlwaysOn ON SyncRst
18 I2C AlwaysOn ON SyncRst
19 UART0 AlwaysOn ON BTSEL[1:0] = 00 – SyncRst (NAND)
BTSEL[1:0] = 01 – SyncRst (OneNAND)
BTSEL[1:0] = 10 – SyncRst (MMC/SD)
BTSEL[1:0] = 11 – Enable (UART)
20 UART1 AlwaysOn ON SyncRst
21 UART2 AlwaysOn ON SyncRst
22 SPI0 AlwaysOn ON SyncRst
23 PWM0 AlwaysOn ON SyncRst
24 PWM1 AlwaysOn ON SyncRst
25 PWM2 AlwaysOn ON SyncRst
26 GPIO AlwaysOn ON SyncRst
27 TIMER0 AlwaysOn ON BTSEL[1:0] = 00 – Enable (NAND)
BTSEL[1:0] = 01 – Enable (OneNAND)
BTSEL[1:0] = 10 – Enable (MMC/SD)
BTSEL[1:0] = 11 – Enable (UART)
28 TIMER1 AlwaysOn ON SyncRst
29 TIMER2 AlwaysOn ON Enable
30 System Module AlwaysOn ON Enable
31 ARM AlwaysOn ON Enable
32 BUS AlwaysOn ON Enable
33 BUS AlwaysOn ON Enable
34 BUS AlwaysOn ON Enable
35 Emulation AlwaysOn ON Enable
36 Test AlwaysOn ON Enable
37 Test AlwaysOn ON Enable
38 Test AlwaysOn ON Enable
39 Reserved Reserved Reserved Reserved
40 MPEG/JPEG AlwaysOn ON SyncRst
Coprocessor (MJCP)
41 VPSS DAC Always On ON SyncRst
7.3.2 Module States
A module can be in one of four states: Disable, Enable, SwRstDisable, or SyncReset.
7.4.2 Module State Transitions
· Wait for the GOSTATx bit in PTSTAT to clear to 0x0. You must wait for any previously initiated
transitions to finish before initiating a new transition.
· Set the NEXT bit in MDCTL[x] to SwRstDisable (0x0), SyncReset (0x1), Disable (0x2), or Enable (0x3).
Note: You may set transitions in multiple NEXT bits in MDCTL[x] in this step.
· Set the GOx bit in PTCMD to 0x1 to initiate the transition(s).
· Wait for the GOSTATx bit in PTSTAT to clear to 0x0. The module is only safely in the new state after
the GOSTATx bit in PTSTAT clears to 0x0.
AINTC Interrupt Connections
Interrupt Acronym Source Interrupt Acronym Source
Number Number
0 VPSSINT0 VPSS - INT0, 32 TINT0 Timer 0 - TINT12
Configurable via
VPSSBL register:
INTSEL
1 VPSSINT1 VPSS - INT1 33 TINT1 Timer 0 - TINT34
2 VPSSINT2 VPSS - INT2 34 TINT2 Timer 1 - TINT12
3 VPSSINT3 VPSS - INT3 35 TINT3 Timer 1 - TINT34
4 VPSSINT4 VPSS - INT4 36 PWMINT0 PWM0
5 VPSSINT5 VPSS - INT5 37 PWMINT1 PWM 1
6 VPSSINT6 VPSS - INT6 38 PWMINT2 PWM2
7 VPSSINT7 VPSS - INT7 39 I2CINT I2C
8 VPSSINT8 VPSS - INT8 40 UARTINT0 UART0
41 UARTINT1 UART1
9 - 11 Reserved for use 42 SPINT0-0 SPI0
with the MJCP
43 SPINT0-1 SPI0
12 USBINT USB OTG Collector 44 GPIO0 GPIO
13 RTOINT or RTO or 45 GPIO1 GPIO
TINT4 Timer 2 - TINT12
SYS.ARM_INTMUX
14 UARTINT2 or UART2 or 46 GPIO2 GPIO
TINT5 Timer 2 - TINT34
15 TINT6 Timer 3 TINT12 47 GPIO3 GPIO
16 CCINT0 EDMA CC Region 0 48 GPIO4 GPIO
17 SPINT1-0 or SPI1 or 49 GPIO5 GPIO
CCERRINT EDMA CC Error
18 SPINT1-1 or SPI1 or 50 GPIO6 GPIO
TCERRINT0 EDMA TC0 Error
19 SPINT2-0 or SPI2 or 51 GPIO7 GPIO
TCERRINT1 EDMA TC1 Error
20 PSCINT PSC - ALLINT 52 GPIO8 GPIO
21 SPINT2-1 SPI2 53 GPIO9 GPIO
22 TINT7 Timer3 - TINT34 54 GPIOBNK0 GPIO
23 SDIOINT0 SDIO0 55 GPIOBNK1 GPIO
24 MBXINT0 or ASP0 or 56 GPIOBNK2 GPIO
MBXINT1 ASP1
25 MBRINT0 or ASP0 or 57 GPIOBNK3 GPIO
MBRINT1 ASP1
26 MMCINT0 MMC/SD0 58 GPIOBNK4 GPIO
27 MMCINT1 MMC/SD1 59 GPIOBNK5 GPIO
28 PWMINT3 PWM3 60 GPIOBNK6 GPIO
29 DDRINT DDR EMIF 61 COMMTX ARMSS
30 AEMIFINT Async EMIF 62 COMMRX ARMSS
31 SDIOINT1 SDIO1 63 EMUINT E2ICE
8.3.3 Vector Table Entry Address Generation
IRQENTRY = EABASE + ((highest priority IRQ EVT# + 1) * SIZE)
FIQENTRY = EABASE + ((highest priority FIQ EVT# + 1) * SIZE)
8.4 INTC Registers
Interrupt Controller (INTC) Registers
Offset Acronym Register Description Section
00h FIQ0 Interrupt Status of INT [31:0] (if mapped to FIQ) Section 8.4.1
04h FIQ1 Interrupt Status of INT [63:32] (if mapped to FIQ) Section 8.4.2
08h IRQ0 Interrupt Status of INT [31:0] (if mapped to IRQ) Section 8.4.3
0Ch IRQ1 Interrupt Status of INT [63:32] (if mapped to IRQ) Section 8.4.4
10h FIQENTRY Entry Address [28:0] for valid FIQ interrupt Section 8.4.5
14h IRQENTRY Entry Address [28:0] for valid IRQ interrupt Section 8.4.6
18h EINT0 Interrupt Enable Register 0 Section 8.4.7
1Ch EINT1 Interrupt Enable Register 1 Section 8.4.8
20h INTCTL Interrupt Operation Control Register Section 8.4.9
24h EABASE Interrupt Entry Table Base Address Section 8.4.10
30h INTPRI0 Interrupt 0-7 Priority select Section 8.4.11
34h INTPRI1 Interrupt 8-15 Priority select Section 8.4.12
38h INTPRI2 Interrupt 16-23 Priority select Section 8.4.13
3Ch INTPRI3 Interrupt 24-31 Priority select Section 8.4.14
40h INTPRI4 Interrupt 32-29 Priority select Section 8.4.15
44h INTPRI5 Interrupt 40-47 Priority select Section 8.4.16
48h INTPRI6 Interrupt 48-55 Priority select Section 8.4.17
4Ch INTPRI7 Interrupt 56-63 Priority select Section 8.4.18
System Control Module
· Device Identification
· Device Configuration
– Pin multiplexing control
– Device boot configuration status
· ARM Interrupt and EDMA Event multiplexing control
· Special Peripheral Status and Control
– Timer64+ control
– USB PHY control
– VPSS clock and Video DAC control and status
– DDR I/O timing control and status
– DDR VTP control
– Clock out circuitry
– GIO de-bounce control
· Power Managment
– Deep Sleep Control
· Bandwidth Management
– Bus master DMA priority control
9.9.1 Bus Master DMA Priority Control
DM355 Master IDs
MSTID Master
0 ARM Instruction
1 ARM Data
2 Reserved
3 Reserved
4-7 Reserved
8 VPSS
9 MPEG/JPEG Coprocessor (MJCP)
10 EDMA
11-15 Reserved
16 EDMA Channel 0 read
17 EDMA Channel 0 write
18 EDMA Channel 1 read
19 EDMA Channel 1 write
20-31 Reserved
32 Reserved
33 Reserved
34 USB
35 Reserved
36 Reserved
37 Reserved
38-63 Reserved
9.10 System Control Register Descriptions
System Module (SYS) Registers
Offset Acronym Register Description Section
0h PINMUX0 PINMUX0 - Pin Mux 0 (Video In) Pin Mux Register Section 9.10.2
4h PINMUX1 PINMUX1 - Pin Mux 1 (Video Out) Pin Mux Register Section 9.10.3
8h PINMUX2 PINMUX2 - Pin Mux 2 (AEMIF) Pin Mux Register Section 9.10.4
Ch PINMUX3 PINMUX3 - Pin Mux 3 (GIO/Misc) Pin Mux Register Section 9.10.5
10h PINMUX4 PINMUX4 - Pin Mux 4 (Misc) Pin Mux Register Section 9.10.6
14h BOOTCFG Boot Configuration Section 9.10.7
18h ARM_INTMUX Multiplexing Control for Interrupts Section 9.10.8
1Ch EDMA_EVTMUX Multiplexing Control for EDMA Events Section 9.10.9
20h DDR_SLEW DDR Slew Rate Section 9.10.10
24h CLKOUT CLKOUT div/out Control Section 9.10.11
28h DEVICE_ID Device ID Section 9.10.12
2Ch VDAC_CONFIG Video DAC Configuration Section 9.10.13
30h TIMER64_CTL TIMER64_CTL - Timer64+ Input Control Section 9.10.14
34h USB_PHY_CTRL USB PHY Control Section 9.10.15
38h MISC Miscellaneous Control Section 9.10.16
3Ch MSTPRI0 Master Priorities Reg0 Section 9.10.17
40h MSTPRI1 Master Priorities Reg1 Section 9.10.18
44h VPSS_CLK_CTRL VPSS Clock Mux Control Section 9.10.19
48h DEEPSLEEP DEEPSLEEP Configuration Section 9.10.20
50h DEBOUNCE0 DEBOUNCE - Debounce for GIO0 Input Section 9.10.21
54h DEBOUNCE1 DEBOUNCE - Debounce for GIO1 Input Section 9.10.21
58h DEBOUNCE2 DEBOUNCE - Debounce for GIO2 Input Section 9.10.21
5Ch DEBOUNCE3 DEBOUNCE - Debounce for GIO3 Input Section 9.10.21
60h DEBOUNCE4 DEBOUNCE - Debounce for GIO4 Input Section 9.10.21
64h DEBOUNCE5 DEBOUNCE - Debounce for GIO5 Input Section 9.10.21
68h DEBOUNCE6 DEBOUNCE - Debounce for GIO6 Input Section 9.10.21
6Ch DEBOUNCE7 DEBOUNCE - Debounce for GIO7 Input Section 9.10.21
70h VTPIOCR VTP IO Control Register Section 9.10.22
DM355 ARM SUBSYSTEM
3.1 DM355 ARM：
· ARM926EJ-S - 32-bit RISC processor
· 16-KB Instruction cache
· 8-KB Data cache
· MMU
· CP15 to control MMU, cache, write buffer, etc.
· Java accelerator
· ARM Internal Memory
– 32-KB built-in RAM
– 8-KB built-in ROM (boot ROM)
· Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
· Features:
– The main write buffer has a 16-word data buffer and a 4-address buffer
– Support for 32/16-bit instruction sets
– Fixed little endian memory format
– Enhanced DSP instructions
3.2 Operating States/Modes
· User mode (USR): Non-privileged mode, usually for the execution of most
application programs.
· Fast interrupt mode (FIQ): Fast interrupt processing
· Interrupt mode (IRQ): Normal interrupt processing
· Supervisor mode (SVC): Protected mode of execution for operating systems
· Abort mode (ABT): Mode of execution after a data abort or a pre-fetch
abort
· System mode (SYS): Privileged mode of execution for operating systems
· Undefined mode (UND): Executing an undefined instruction causes the ARM
to enter undefined mode.
可以从其它MODE进入privileged modes (system or supervisor)，如从USER
MODE要进入privileged modes 可以发出软件中断（SWI），IRQ或FIQ来进行
不同的模式需设置不同的STACK，STACK POINT自动指到其模式的SP
3.3 Processor Status Registers
processor status register
(PSR)设置中断能动禁止，操作模式设置。PSR[7：0]控制位，PSR[27：8]保留，PSR
[31:28]状态位。PSR[7:0]如下：
· Bit 7 - I bit: Disable IRQ (I =1) or enable IRQ (I = 0)
· Bit 6 - F bit: Disable FIQ (F = 1) or enable FIQ (F = 0)
· Bit 5 - T bit: Controls whether the processor is in thumb mode (T = 1)
or ARM mode (T = 0)
· Bits 4:0 Mode: Controls the mode of operation of the processor
– PSR [4:0] = 10000 : User mode
– PSR [4:0] = 10001 : FIQ mode
– PSR [4:0] = 10010 : IRQ mode
– PSR [4:0] = 10011 : Supervisor mode
– PSR [4:0] = 10111 : Abort mode
– PSR [4:0] = 11011 : Undefined mode
– PSR [4:0] = 11111 : System mode
PSR[31:28]反映算术单员ALU的状态：
· Bit 31 - N bit: Negative or less than
· Bit 30 - Z bit: Zero
· Bit 29 - C bit: Carry or borrow
· Bit 28 - V bit: Overflow or underflow
3.4 Exceptions and Exception Vectors例外及其向量
例外可有以下方式产生
· Reset exception: processor reset
· FIQ interrupt: fast interrupt
· IRQ interrupt: normal interrupt
· Abort exception: abort indicates that the current memory access could
not be completed. The abort
could be a pre-fetch abort or a data abort.
· SWI interrupt: use software interrupt to enter supervisor mode.
· Undefined exception: occurs when the processor executes an undefined
instruction
以上由高到低优先权为：reset, data abort, FIQ, IRQ, pre-fetch
abort, undefined instruction及SWI，undefined instruction及SWI优先权一样。
依靠CP15寄存器中VINTH来设置向量表位置：0x00000000 (VINTH = 0) or at
address 0xFFFF0000 (VINTH = 1). .
注： 以上只是ARM926EJ-S
core的特性，在DMSOC中，0xFFFF0000处没有内存，所以并不设置VINTH
Table 3-1. Exception Vector Table for ARM
Vector Offset Address Exception Mode on entry I Bit State
on Entry F Bit State on Entry
0h Reset Supervisor
Set Set
04h fined instruction Undefined
Set Unchanged
08h Software interrupt Supervisor
Set Unchanged
0Ch Pre-fetch abort Abort
Set Unchanged
10h Data abort Abort
Set Unchanged
14h Reserved -
- -
18h IRQ IRQ
Set Unchanged
1Ch FIQ FIQ
Set Set
3.5 The 16-BIS/32-BIS Concept
16位指令集是32位的缩减，相同条件下，16位的代码是32位的65%，当连接16
MEMORY进其性能是32位的1.6倍
3.6 Coprocessor 15 (CP15)
system control coprocessor
(CP15)用来设置指令及数据caches，Tightly-Coupled Memories (TCMs), Memory
Management Units (MMUs), and many system functions。CP15寄存器仅能由MRC
and MCR
指令在privileged mode下访问。
3.6.1 Addresses in an ARM926EJ-S System
Different Address Types in ARM Syste
Domain ARM9EJ-S Caches and MMU
TCM and AMBA Bus
Address type Virtual Address (VA) Modified Virtual Address (MVA) P
hysical Address (PA)
The VA of the instruction is issued by the ARM9EJ-S core.
The VA is translated to the MVA. The Instruction Cache (Icache) and Memory
Management Unit (MMU)
detect the MVA.
If the protection check carried out by the MMU on the MVA does not abort
and the MVA tag is in the
Icache, the instruction data is returned to the ARM9EJ-S core.
If the protection check carried out by the MMU on the MVA does not abort,
and the MVA tag is not in
the cache, then the MMU translates the MVA to produce the PA.
3.6.2 Memory Management Unit
3.6.3 Caches and Write Buffer
· An Instruction cache (Icache) 16KB
· A Data cache (Dcache) 8KB
· A write buffer 17 bytes
3.7 Tightly Coupled Memory
TCM主要用来作实时及关键代码
DM355 supports both instruction TCM (I-TCM) and data TCM (D-TCM). The
instruction TCM is located at
0x0000:0000 to 0x0000:7FFF. The data TCM is located at 0x0001:0000 to
0x0001:9FFF
--------------------------------------------------------------------------------------
ITCM/DTCM Memory Map
I-TCM Address D-TCM Address Size
(Bytes) Description
0x0000 :0000 - 0x0000 :3FFF 0x0001 :0000 - 0x0001 :3FFF
16K IRAM0
0x0000 :4000 - 0x0000 :7FFF 0x0001 :4000 - 0x0001 :7FFF
16K IRAM1
0x0000 :8000 - 0x0000 :9FFF 0x0001 :8000 - 0x0001 :9FFF
8K ROM
0x0000 :A000 - 0x0000 :FFFF 0x0001 :A000 - 0x0001 :FFFF
24K Reserved
------------------------------------------------------------------------------------------
TCM状态可从CP15 reg 0读取
TCM状态寄存器
31
17 16
SBZ/UNP
DTCM
15
1 0
SBZ/UNP
ITCM
------------------------------------------------------------------------------------------
TCM数据寄存器
31
16
ADDRESS
15 12 11 6 5
2 1 0
ADDRESS S BZ/UNP
SIZE 0 ENB
----------------------------------------------------------------------------------------
ITCM/DTCM Size Encoding
Binary Code Size
0000 0 KB / absent
0001,0010 Reserved
0011 4 KB
0100 8 KB
0101 16 KB
0110 32 KB
0111 64 KB
1000 128 KB
1001 256 KB
1010 512 KB
1011 1 MB
11xx Reserved
注：
用0x00010019 to enable DTCM for DM355: 0x00010000 (base address) |
0b0110 << 2 (size) | 1 (enable)
3.8 Embedded Trace Support
Embedded Trace Macrocell (ETM),Embedded Trace Buffer (ETB).
注：The DM355 trace port is not pinned out. Instead, it is connected to a
4KB Embedded Trace
Buffer. ETB enabled debug tools are required to read/interpret the
captured trace data.
Trace Port Analyzer (TPA)
ETM Part Descriptions
ETM Part Descriptions
Trace Port: The trace port allows you to debug the
PRocessor.
The trace port has a protocol that has been
developed to provide a real-time trace
capability for processor cores that are deeply embedded in
large ASIC designs. This is beneficial to developers
and manufacturers when it is not possible to
determine how the processor core is operating by only observing the pins
of the ASIC.
Triggering Facilities:
An extensible ETM specification exists to specify the exact set of trigger
resources required for a
particular application. Resources include address and data comparators,
counters, and
sequencers.
Davinci内核编译常用命令
内核编译常用命令
DM6446设置内核为默认配置模式：
make ARCH=arm CROSS_COMPILE=arm_v5t_le- davinci_dm644x_defconfig
make ARCH=arm CROSS_COMPILE=arm_v5t_le- checksetconfig
DM6446设置内核为默认配置模式：
make ARCH=arm CROSS_COMPILE=arm_v5t_le- davinci_dm644x_defconfig
make ARCH=arm CROSS_COMPILE=arm_v5t_le- checksetconfig
DM355设置内核为默认配置模式：
make ARCH=arm CROSS_COMPILE=arm_v5t_le- davinci_dm355_evm_defconfig
make ARCH=arm CROSS_COMPILE=arm_v5t_le- checksetconfig
进入配置菜单，更改内核配置选项：
make ARCH=arm CROSS_COMPILE=arm_v5t_le- menuconfig
内核镜像编译命令：
make ARCH=arm CROSS_COMPILE=arm_v5t_le- uImage
内核模块编译命令：
ARCH=arm CROSS_COMPILE=arm_v5t_le- modules
如果遇到镜像编译时找不到mkimage命令的，执行如下命令，再执行make命令
export
PATH=$PATH:/opt/mv_pro_4.0.1/montavista/pro/bin（编译内核所需的gcc所在路径）
chmod a+x
/opt/mv_pro_4.0.1/montavista/pro/bin/mkimage（mkimage所在路径）
make ARCH=arm CROSS_COMPILE=arm_v5t_le- uImage
如若还不行，则：
打开/home/davinci/ICETEKWork/lsp/ti-davinci/scripts/mkuboot.sh文件，将其中的MKIMAGE直接赋值为mkimage的绝对路径，我的为：MKIMAGE=/opt/mv_pro_4.0/montavista/pro/bin/mkimage，然后重新运行编译内核命令即可。。。
Davinci U-Boot系列之一：U-Boot简介
TI推出的数字多媒体平台DM系列，集成了ARM与DSP双核处理器：DSP处理器运行DSP/BIOS操作系统，负责音视频编解码算法以及其他图形处理算法；ARM处理器运行MontaVista
Linux操作系统，负责设备初始化、用户图形界面管理。ARM处理器端的MontaVista
Linux加载启动，需要有Bootloader完成内核由Flash空间加载到DDR空间并启动Linux系统。Bootloader就是在OS内核运行之前运行的一段程序，通过这段引导程序，初始化硬件设备、建立内存空间映射图，使系统的软硬件环境处于一个合适的状态，为OS内核的启动做好准备。目前TI的DM6446平台采用U-Boot作为Bootloader引导程序。
一、U-Boot简介
U-Boot，全称Universal Boot Loader,是遵循GPL(General Public
License)条款的开放源码项目。U-Boot不仅仅支持嵌入式Linux系统的引导，还支持NetBSD,VxWorks,QNX,RTEMS,artos,LynxOS嵌入式操作系统。U-Boot支持PowerPC,MIPS,X86,ARM,NIOS,XScale等诸多常用系统的处理器。U-Boot项目的开发目标，即是支持尽可能多的嵌入式处理器和嵌入式操作系统。
U-Boot的特点：
> 开放源码;
> 支持多种嵌入式操作系统内核，如：式LinuxNetBSD,VxWorks,QNX,RTEMS,artos,LynxOS;
> 支持多个处理器系列，如PowerPC,MIPS,X86,ARM,NIOS,XScale;
> 较高的可靠性和稳定性;
> 高度灵活的功能设置，适合U-Boot调试、操作系统不同引导要求等;
> 丰富的设备驱动源码，如串口、以太网、SDRAM、FLASH、EEPROM、RTC、键盘等;
> 较为丰富的开发调试文档与强大的网络技术支持。
二、U-Boot目录结构
> board: 目标板相关文件，主要包含SDRAM,FLASH驱动;
> common:独立于处理器体系结构的通用代码，如内存大小探测与故障检测;
> cpu:
> 与处理器相关的文件。如mpc8xx子目录下含串口、网口、LCD驱动及中断初始化等文件;
> driver: 通用设备驱动，如CFI FLASH 驱动(目前对INTEL FLASH支持较好);
> doc:U-Boot的说明文档;
> examples:U-Boot下运行的实例程序，如hello_world.c,timer.c;
> include:
> U-Boot头文件，configs子目录下与目标板相关的配置头文件是移植过程中经常要修改的文件;
> lib_xxx:
> 处理器体系相关的文件，如lib_ppc,lib_arm目录分别包含与PowerPC,ARM体系结构相关的文件;
> net: 网络功能相关的文件目录，如bootp,nfs,tftp;
> post: 上电自检文件目录，尚待进一步完善;
> rtc: RTC驱动程序;
> tools: 用于创建U-Boot S-RECORD和BIN镜像文件的工具;
U-Boot目前已经支持TI的DM6446平台，在board/davinci目录下为devem目标板相关文件，其中包含了网络、flash等的驱动程序。
Davinci U-Boot系列之二：U-Boot在SEED-DVS6446平台上的应用
SEED-DVS6446平台采用U-Boot-1.2.0版本，针对NAND
Flash、Net、DDR驱动修改，并提供更多的U-Boot命令支持。下面以SEED-DVS6446平台为例，说明U-Boot在该平台上的常用配置使用。
一、U-Boot启动
1.软件配置
打开串口超级终端(PC超级终端、Hyperterminal、Teraterm),配置相关参数如下：
> 波特率：115200
> 数据位：8
> 奇偶较验：None
> 停止位：1
> 数据流控制：None
2.硬件配置
> DB9串口线一端连接DAVINCI平台串口，另一端连接PC机串口；
> DAVINCI平台的视频采集口连接摄像头或者DVD作为视频输入；
> DAVINCI平台的视频输出口连接显示设备；
> DAVINCI平台的网络接口通过网线连接至路由器等网络接口，或者通过直通线与
PC机网口连接；
> DAVINCI平台采用5V-5A电源供电，启动系统。
此时可以在串口超级终端看到DVS6446平台的一些相关信息，比如ARM,DDR时钟频率，U-Boot版本等等。
二、U-Boot通过TFTP下载内核启动并挂载网络文件系统
TFTP下载内核启动挂载网络文件系统方式，即通过TFTP服务器下载内核启动，文件系统挂载到Linux服务器下的已经搭建好的/opt/nfs文件系统目录下。过程如下：
1.SEED-DVS6446上电启动，显示上述启动信息，当显示"hit any key to stop
autoboot:
3"时按下回车键，中断系统自动启动，进行启动参数配置，此时显示如下提示符：SEED-DVS6446_v1.2#:
;
2.配置启动参数，在提示符下输入以下配置参数：setenv bootargs mem=120M
console=ttyS0,115200n8 root=/dev/nfs noinitrd rw ip=dhcp nfsroot=nfs
ip=/opt/nfs video=dm64xxfbutput=pal
3.设置tftp服务器的IP地址和DVS6446的IP地址，在提示符下分别输入如下配置(tftp服务器的IP地址和DVS6446的IP地址，根据实际应用配置)：
setenv serverip _._._._
setenv ipaddr _._._._
4.下载内核并启动(默认用户已经将内核文件uImage复制到tftp服务的根目录下),在提示符下配置下载启动：
tftp 0x80800000 uImage;bootm 0x80800000
5.配置完成系统启动，并自动挂载网络文件系统，启动完毕显示等待登录信息。
三、通过U-Boot配置参数实现VGA视频输出与复合视频输出的配置
SEED-DVS6446支持复合视频与VGA视频输出显示，默认采用复合视频输出，用户可以通过U-Boot中的参数配置实现VGA输出。以TFTP下载内核启动挂载网络文件系统方式为例，详细步骤如下：
1.SEED-DVS6446 U-Boot启动，显示启动信息，当显示"hit any key to stop
autoboot:
3"时按下回车键，中断系统自动启动，进行启动参数配置，此时显示如下提示符：SEED-DVS6446_v1.2#:
;
2.配置启动参数，在提示符下输入以下配置参数：setenv bootargs mem=120M
console=ttyS0,115200n8 root=/dev/nfs noinitrd rw ip=dhcp nfsroot=nfs
ip=/opt/nfs video=dm64xxfb format=vgautput=pal
3.设置tftp服务器的IP地址和DVS6446的IP地址，在提示符下分别输入如下配置：
setenv serverip _._._._
setenv ipaddr _._._._
4.下载内核并启动，在提示符下配置下载启动：
tftp 0x80800000 uImage;bootm 0x80800000
5.配置完成系统启动，并自动挂载网络文件系统，将VGA接口同SEED-DVS6446平台的VGA输出口连接，启动完毕即显示等待登录信息，VGA显示器左上角显示Monta
Vista Linux的图标。
四、从CCS直接烧录到DDR情况下，不需要U-Boot，此时cmd的通用脚本文件如下：
-lrts32e.lib
-l..\..\csl\arm\lib\Debug\csl_davinciArm9.lib
-l..\..\lib\davincievmbsl.lib
-stack 0x00000800
-heap 0x00000800
MEMORY
{
IRAM: o = 0x00000000 l = 0x00004000
DRAM: o = 0x00008000 l = 0x00004000
AEMIF: o = 0x02000000 l = 0x02000000
DDR2: o = 0x80000000 l = 0x08000000
}
SECTIONS
{
.bss > DDR2
.cinit > DDR2
.cio > DDR2
.const > DDR2
.stack > DDR2
.sysmem > DDR2
.text > DDR2
.ddr2 > DDR2
}
Davinci U-Boot系列之三：U-Boot常用命令和常用环境变量
U-Boot常用命令
?：
得到所有命令列表或者列出某个命令的帮助。
用法：? [command ...]
说明：列出命令的帮助信息，当不带参数时，列出所有命令及简要说明。
help：
同?
printenv：
打印环境变量。
用法：printenv [name]
说明：name一般是Hiboot环境变量的名字，也可以是用户自定义的变量；当value为空时，删除变量
"name", 否则设置变量"name",且值为"value".
saveenv：
保存变量。
用法：saveenv
说明：保存变量及其值到flash.
ping：
用于简单判断目标机网络状态或本机网络工作状态。
tftp：
从tftp服务器中下载文件至RAM或者Flash中。
用法：tftp addr file
说明：将file文件下载到地址为addr的RAM或者Flash中。注意：使用tftp时，必须先设置好网络配置，使用setenv配置ipaddr、netmask、serverip参数。
cp：
拷贝内存。
用法：cp[.b,.w,.l]source target count.
说明：把地址为source的内存区域的值，拷贝到地址target的内存区域，区域的大小为count，source和target可以是SDRAM的地址访问，也可以是flash的地址范围，实际拷贝的大小，因命令的不同而不同。cp.b拷贝1xcount
bytes,简单使用cp时，默认为4xcount bytes.
go：
跳转到指定地址，执行代码。
用法：go addr [arg ...]
说明：执行地址addr处的二进制代码，可传递arg参数。
reset：
复位cpy处理器
用法：reset
bootm：
设置运行环境，并开始执行二进制代码。
用法：bootm [addr[arg ...]]
说明：执行addr处的代码，要求二进制代码为mkimage处理过的二进制文件。
erase：
擦除Flash内容.
用法1：erase start end.
说明：擦除地址从start到地址为end区域的内容。
注意：flash的擦除操作必须以块为最小单位，因此地址start必须为某块的其实地址，end地址则为某块的结束地址，如flash的基地址为0x34000000,块大小为0x20000,则操作erase
0x34000000 0x3401FFFF为可操作的，而erase 0x34000003 0x3401FFFF或者erase
0x34000000 0x3401FF00均不可操作。
用法2：erase N:SF[-SL].
说明：擦除第N块flash的从扇区SF到SL扇区的内容。
用法3：erase bank N.
擦除第N块flash的内容。
用法4：erase all
说明：擦除所有flash的内容。
nand erase：
擦除nand flash内容
用法：nand erase start size
nand write：
用来将内存数据写入nand flash
用法：nand write sram_addr start size
说明：将内存sram_addr处的数据写入nand flash
start地址开始的空间，写入大小为size.
U-Boot常用环境变量
ipaddr:
设置DVS6446平台的IP地址
说明：setenv ipaddr 192.168.253.53
serverip:
设置服务器ip地址，多用于tftp中
说明：setenv serverip 192.168.253.33
bootargs:
启动OS的启动参数
说明：setenv bootargs mem=120M console=ttys0,115200n8 ...
解释：设置传递参数，如内存大小，控制台，根文件系统等。
bootcmd:
设置自动及执行命令。启动延时根据bootdelay的值，若没有设置bootdelay,默认延时3秒
说明：setenv bootcmd bootm
0x23450000,即设置启动后自动执行0x23450000处的代码。
bootdelay:
设置自启动延时时间，单位为秒。只有当bootcmd变量被设置后，该变量才有效。改变了值范围为大于等于-1的整数，当设置为-1时，关闭自启动的功能。
说明：setenv bootdelay 4 ; 设置自启动延时4秒
说明：setenv bootdelay -1; 关闭自启动功能
提示：在延时时间内可按任意键切换到命令行模式。注意，在产品开发调试阶段请勿设置延时时间为0，若设置，可以在启动瞬间使用CTRL+C中断程序而进入命令行模式。
netmask:
设置子网掩码。
说明：setenv netmask 255.255.255.0
gatewayip:
设置网关。
说明：setenv gatewayip 192.168.253.1
ethaddr:
设置以太网网卡MAC地址。
说明：setenv ethaddr xx: xx: xx: xx: xx: xx
注意：设置ethaddr后，应运行saveenv,重启才能使MAC地址配置有效。
声明：以上文章来自http://www.tichinese.com/bbs/viewthread.php?tid=151&extra=page%3D9，此处只作为学习之用
附：
uboot常用命令
显示环境变量： printenv
保存环境变量： saveenv
设置内核文件名： setenv bootfile
uImage-dm355，其中uImage-dm355为对应的文件名
设置内核启动方式：
1，从网络启动：setenv bootcmd 'tftp;bootm'
2，从FLASH启动
对于DM355: setenv bootcmd 'nboot 0x80700000 0
0x400000;bootm'
对于DM6446: setenv bootcmd 'bootm 0x2040000'
设置bootargs：
DM355:
文件系统：NFS，文件系统的路径：nfsroot=192.168.1.55:/home/filesys；IP:DHCP；输入：模拟输入；输出NTSC
setenv bootargs console=ttyS0,115200n8 noinitrd rw ip=dhcp
root=/dev/nfs
nfsroot=192.168.1.55:/home/filesys,nolock mem=100M
v4l2_video_capture=:device=TVP5146
video=dm64xxfb:output=ntsc
文件系统：NFS，文件系统的路径：nfsroot=192.168.1.55:/home/filesys；IP:DHCP；输入：数字CMOS输入；输出PAL
setenv bootargs console=ttyS0,115200n8 noinitrd rw ip=dhcp
root=/dev/nfs
nfsroot=192.168.1.55:/home/filesys,nolock mem=100M
v4l2_video_capture=:device=MT9T001
video=dm64xxfb:output=pal
文件系统：本地FLASH；IP:固定IP；输入：数字CMOS输入；输出PAL
setenv bootargs console=ttyS0,115200n8 noinitrd rw
rootfstype=yaffs2
ip=192.168.1.11:192.168.1.55:192.168.1.1:255.255.255.0:192.168.1.11::off
root=/dev/mtdblock3 nolock
mem=90M v4l2_video_capture=:device=MT9T001
video=dm64xxfb:output=pal
DM6446:
文件系统：NFS，文件系统的路径：nfsroot=192.168.1.55:/home/filesys；IP:DHCP；输入：模拟输入；输出PAL
setenv bootargs console=ttyS0,115200n8 noinitrd rw ip=dhcp
root=/dev/nfs
nfsroot=192.168.1.55:/home/filesys,nolock mem=38M
v4l2_video_capture=:device=TVP5146
video=dm64xxfb:output=pal
文件系统：本地硬盘；IP:DHCP；输入：模拟输入；输出PAL
setenv bootargs console=ttyS0,115200n8 noinitrd rw ip=dhcp
root=/dev/hda1
nfsroot=192.168.1.55:/home/filesys,nolock mem=38M
v4l2_video_capture=:device=TVP5146
video=dm64xxfb:output=pal
文件系统：NFS，文件系统的路径：nfsroot=192.168.1.55:/home/filesys；IP:固定IP；输入：模拟输入；输出NTSC
setenv bootargs console=ttyS0,115200n8 noinitrd rw
ip=192.168.1.240::192.168.1.2 root=/dev/nfs
nfsroot=192.168.1.55:/home/filesys, nolock mem=38M
video=dm64xxfb:output=ntsc v4l2_video_capture=:device=TVP5146
文件系统：本地硬盘；IP:固定IP；输入：模拟输入；输出PAL
setenv bootargs console=ttyS0,115200n8 noinitrd rw
ip=192.168.1.240::192.168.1.2 root=/dev/hda1
nfsroot=192.168.1.55:/home/filesys,nolock mem=38M
v4l2_video_capture=:device=TVP5146
video=dm64xxfb:output=pal
烧录内核至FLASH
DM355:
tftp 80700000 uImage-dm355:其中uImage-dm355为对应的文件名
nand erase 400000 200000
nand write 0x80700000 0x400000 0x200000
setenv bootcmd 'nboot 0x80700000 0 0x400000;bootm'
DM6446
tftp
erase 0x2040000
+0x157fb0(其中0x157fb0为对应内核文件的大小，通过tftp命令可以统计出来)
setenv bootcmd 'bootm 0x2040000'
cp.b 0x80700000 0x2040000
0x157fb0(其中0x157fb0为对应内核文件的大小，通过tftp命令可以统计出来)
LINUX 常用命令
路径切换命令：
显示当前所在目录路径
pwd
进入/root/encode目录
cd /root/encode
如果目前所在目录是/root
则输入：
cd encode即可进入/root/encode目录
驱动挂载命令：
查看系统上挂载的移动设备
fdisk -l
将USB设备（/dev/sda1）mount到mnt/usb目录下
mount /dev/sda1 /mnt/usb
拷贝命令：
从目录A(/root/encode)拷贝一文件到目录B(mnt/usb)
cp /root/encode/test.mpeg4 mnt/usb
进程终止命令
显示系统进程：ps -a
终止某进程： kill 996(996为目前某进程的PID号）
应用程序执行命令
执行应用程序encode
./encode
后台执行应用程序encode
./encode&(在DM355脱机方式，建议通过此方式执行应用程序，方可以通过kill命令进行进程的终止)
打包命令
tar -zcf A.tar.gz B（其中B为欲打包的目录，A为压缩包的命名）
解包命令
tar -xzf ti-davinci.tar.gz（其中
ti-davinci.tar.gz欲解包的命名，解压在当前目录
Linux操作系统，负责设备初始化、用户图形界面管理。ARM处理器端的MontaVista
Linux加载启动，需要有Bootloader完成内核由Flash空间加载到DDR空间并启动Linux系统。Bootloader就是在OS内核运行之前运行的一段程序，通过这段引导程序，初始化硬件设备、建立内存空间映射图，使系统的软硬件环境处于一个合适的状态，为OS内核的启动做好准备。目前TI的DM6446平台采用U-Boot作为Bootloader引导程序。
一、U-Boot简介
U-Boot，全称Universal Boot Loader,是遵循GPL(General Public
License)条款的开放源码项目。U-Boot不仅仅支持嵌入式Linux系统的引导，还支持NetBSD,VxWorks,QNX,RTEMS,artos,LynxOS嵌入式操作系统。U-Boot支持PowerPC,MIPS,X86,ARM,NIOS,XScale等诸多常用系统的处理器。U-Boot项目的开发目标，即是支持尽可能多的嵌入式处理器和嵌入式操作系统。
U-Boot的特点：
> 开放源码;
> 支持多种嵌入式操作系统内核，如：式LinuxNetBSD,VxWorks,QNX,RTEMS,artos,LynxOS;
> 支持多个处理器系列，如PowerPC,MIPS,X86,ARM,NIOS,XScale;
> 较高的可靠性和稳定性;
> 高度灵活的功能设置，适合U-Boot调试、操作系统不同引导要求等;
> 丰富的设备驱动源码，如串口、以太网、SDRAM、FLASH、EEPROM、RTC、键盘等;
> 较为丰富的开发调试文档与强大的网络技术支持。
二、U-Boot目录结构
> board: 目标板相关文件，主要包含SDRAM,FLASH驱动;
> common:独立于处理器体系结构的通用代码，如内存大小探测与故障检测;
> cpu:
> 与处理器相关的文件。如mpc8xx子目录下含串口、网口、LCD驱动及中断初始化等文件;
> driver: 通用设备驱动，如CFI FLASH 驱动(目前对INTEL FLASH支持较好);
> doc:U-Boot的说明文档;
> examples:U-Boot下运行的实例程序，如hello_world.c,timer.c;
> include:
> U-Boot头文件，configs子目录下与目标板相关的配置头文件是移植过程中经常要修改的文件;
> lib_xxx:
> 处理器体系相关的文件，如lib_ppc,lib_arm目录分别包含与PowerPC,ARM体系结构相关的文件;
> net: 网络功能相关的文件目录，如bootp,nfs,tftp;
> post: 上电自检文件目录，尚待进一步完善;
> rtc: RTC驱动程序;
> tools: 用于创建U-Boot S-RECORD和BIN镜像文件的工具;
U-Boot目前已经支持TI的DM6446平台，在board/davinci目录下为devem目标板相关文件，其中包含了网络、flash等的驱动程序。
Davinci U-Boot系列之二：U-Boot在SEED-DVS6446平台上的应用
SEED-DVS6446平台采用U-Boot-1.2.0版本，针对NAND
Flash、Net、DDR驱动修改，并提供更多的U-Boot命令支持。下面以SEED-DVS6446平台为例，说明U-Boot在该平台上的常用配置使用。
一、U-Boot启动
1.软件配置
打开串口超级终端(PC超级终端、Hyperterminal、Teraterm),配置相关参数如下：
> 波特率：115200
> 数据位：8
> 奇偶较验：None
> 停止位：1
> 数据流控制：None
2.硬件配置
> DB9串口线一端连接DAVINCI平台串口，另一端连接PC机串口；
> DAVINCI平台的视频采集口连接摄像头或者DVD作为视频输入；
> DAVINCI平台的视频输出口连接显示设备；
> DAVINCI平台的网络接口通过网线连接至路由器等网络接口，或者通过直通线与
PC机网口连接；
> DAVINCI平台采用5V-5A电源供电，启动系统。
此时可以在串口超级终端看到DVS6446平台的一些相关信息，比如ARM,DDR时钟频率，U-Boot版本等等。
二、U-Boot通过TFTP下载内核启动并挂载网络文件系统
TFTP下载内核启动挂载网络文件系统方式，即通过TFTP服务器下载内核启动，文件系统挂载到Linux服务器下的已经搭建好的/opt/nfs文件系统目录下。过程如下：
1.SEED-DVS6446上电启动，显示上述启动信息，当显示"hit any key to stop
autoboot:
3"时按下回车键，中断系统自动启动，进行启动参数配置，此时显示如下提示符：SEED-DVS6446_v1.2#:
;
2.配置启动参数，在提示符下输入以下配置参数：setenv bootargs mem=120M
console=ttyS0,115200n8 root=/dev/nfs noinitrd rw ip=dhcp nfsroot=nfs
ip=/opt/nfs video=dm64xxfbutput=pal
3.设置tftp服务器的IP地址和DVS6446的IP地址，在提示符下分别输入如下配置(tftp服务器的IP地址和DVS6446的IP地址，根据实际应用配置)：
setenv serverip _._._._
setenv ipaddr _._._._
4.下载内核并启动(默认用户已经将内核文件uImage复制到tftp服务的根目录下),在提示符下配置下载启动：
tftp 0x80800000 uImage;bootm 0x80800000
5.配置完成系统启动，并自动挂载网络文件系统，启动完毕显示等待登录信息。
三、通过U-Boot配置参数实现VGA视频输出与复合视频输出的配置
SEED-DVS6446支持复合视频与VGA视频输出显示，默认采用复合视频输出，用户可以通过U-Boot中的参数配置实现VGA输出。以TFTP下载内核启动挂载网络文件系统方式为例，详细步骤如下：
1.SEED-DVS6446 U-Boot启动，显示启动信息，当显示"hit any key to stop
autoboot:
3"时按下回车键，中断系统自动启动，进行启动参数配置，此时显示如下提示符：SEED-DVS6446_v1.2#:
;
2.配置启动参数，在提示符下输入以下配置参数：setenv bootargs mem=120M
console=ttyS0,115200n8 root=/dev/nfs noinitrd rw ip=dhcp nfsroot=nfs
ip=/opt/nfs video=dm64xxfb format=vgautput=pal
3.设置tftp服务器的IP地址和DVS6446的IP地址，在提示符下分别输入如下配置：
setenv serverip _._._._
setenv ipaddr _._._._
4.下载内核并启动，在提示符下配置下载启动：
tftp 0x80800000 uImage;bootm 0x80800000
5.配置完成系统启动，并自动挂载网络文件系统，将VGA接口同SEED-DVS6446平台的VGA输出口连接，启动完毕即显示等待登录信息，VGA显示器左上角显示Monta
Vista Linux的图标。
四、从CCS直接烧录到DDR情况下，不需要U-Boot，此时cmd的通用脚本文件如下：
-lrts32e.lib
-l..\..\csl\arm\lib\Debug\csl_davinciArm9.lib
-l..\..\lib\davincievmbsl.lib
-stack 0x00000800
-heap 0x00000800
MEMORY
{
IRAM: o = 0x00000000 l = 0x00004000
DRAM: o = 0x00008000 l = 0x00004000
AEMIF: o = 0x02000000 l = 0x02000000
DDR2: o = 0x80000000 l = 0x08000000
}
SECTIONS
{
.bss > DDR2
.cinit > DDR2
.cio > DDR2
.const > DDR2
.stack > DDR2
.sysmem > DDR2
.text > DDR2
.ddr2 > DDR2
}
Davinci U-Boot系列之三：U-Boot常用命令和常用环境变量
U-Boot常用命令
?：
得到所有命令列表或者列出某个命令的帮助。
用法：? [command ...]
说明：列出命令的帮助信息，当不带参数时，列出所有命令及简要说明。
help：
同?
printenv：
打印环境变量。
用法：printenv [name]
说明：name一般是Hiboot环境变量的名字，也可以是用户自定义的变量；当value为空时，删除变量
"name", 否则设置变量"name",且值为"value".
saveenv：
保存变量。
用法：saveenv
说明：保存变量及其值到flash.
ping：
用于简单判断目标机网络状态或本机网络工作状态。
tftp：
从tftp服务器中下载文件至RAM或者Flash中。
用法：tftp addr file
说明：将file文件下载到地址为addr的RAM或者Flash中。注意：使用tftp时，必须先设置好网络配置，使用setenv配置ipaddr、netmask、serverip参数。
cp：
拷贝内存。
用法：cp[.b,.w,.l]source target count.
说明：把地址为source的内存区域的值，拷贝到地址target的内存区域，区域的大小为count，source和target可以是SDRAM的地址访问，也可以是flash的地址范围，实际拷贝的大小，因命令的不同而不同。cp.b拷贝1xcount
bytes,简单使用cp时，默认为4xcount bytes.
go：
跳转到指定地址，执行代码。
用法：go addr [arg ...]
说明：执行地址addr处的二进制代码，可传递arg参数。
reset：
复位cpy处理器
用法：reset
bootm：
设置运行环境，并开始执行二进制代码。
用法：bootm [addr[arg ...]]
说明：执行addr处的代码，要求二进制代码为mkimage处理过的二进制文件。
erase：
擦除Flash内容.
用法1：erase start end.
说明：擦除地址从start到地址为end区域的内容。
注意：flash的擦除操作必须以块为最小单位，因此地址start必须为某块的其实地址，end地址则为某块的结束地址，如flash的基地址为0x34000000,块大小为0x20000,则操作erase
0x34000000 0x3401FFFF为可操作的，而erase 0x34000003 0x3401FFFF或者erase
0x34000000 0x3401FF00均不可操作。
用法2：erase N:SF[-SL].
说明：擦除第N块flash的从扇区SF到SL扇区的内容。
用法3：erase bank N.
擦除第N块flash的内容。
用法4：erase all
说明：擦除所有flash的内容。
nand erase：
擦除nand flash内容
用法：nand erase start size
nand write：
用来将内存数据写入nand flash
用法：nand write sram_addr start size
说明：将内存sram_addr处的数据写入nand flash
start地址开始的空间，写入大小为size.
U-Boot常用环境变量
ipaddr:
设置DVS6446平台的IP地址
说明：setenv ipaddr 192.168.253.53
serverip:
设置服务器ip地址，多用于tftp中
说明：setenv serverip 192.168.253.33
bootargs:
启动OS的启动参数
说明：setenv bootargs mem=120M console=ttys0,115200n8 ...
解释：设置传递参数，如内存大小，控制台，根文件系统等。
bootcmd:
设置自动及执行命令。启动延时根据bootdelay的值，若没有设置bootdelay,默认延时3秒
说明：setenv bootcmd bootm
0x23450000,即设置启动后自动执行0x23450000处的代码。
bootdelay:
设置自启动延时时间，单位为秒。只有当bootcmd变量被设置后，该变量才有效。改变了值范围为大于等于-1的整数，当设置为-1时，关闭自启动的功能。
说明：setenv bootdelay 4 ; 设置自启动延时4秒
说明：setenv bootdelay -1; 关闭自启动功能
提示：在延时时间内可按任意键切换到命令行模式。注意，在产品开发调试阶段请勿设置延时时间为0，若设置，可以在启动瞬间使用CTRL+C中断程序而进入命令行模式。
netmask:
设置子网掩码。
说明：setenv netmask 255.255.255.0
gatewayip:
设置网关。
说明：setenv gatewayip 192.168.253.1
ethaddr:
设置以太网网卡MAC地址。
说明：setenv ethaddr xx: xx: xx: xx: xx: xx
注意：设置ethaddr后，应运行saveenv,重启才能使MAC地址配置有效。
声明：以上文章来自http://www.tichinese.com/bbs/viewthread.php?tid=151&extra=page%3D9，此处只作为学习之用
附：
uboot常用命令
显示环境变量： printenv
保存环境变量： saveenv
设置内核文件名： setenv bootfile
uImage-dm355，其中uImage-dm355为对应的文件名
设置内核启动方式：
1，从网络启动：setenv bootcmd 'tftp;bootm'
2，从FLASH启动
对于DM355: setenv bootcmd 'nboot 0x80700000 0
0x400000;bootm'
对于DM6446: setenv bootcmd 'bootm 0x2040000'
设置bootargs：
DM355:
文件系统：NFS，文件系统的路径：nfsroot=192.168.1.55:/home/filesys；IP:DHCP；输入：模拟输入；输出NTSC
setenv bootargs console=ttyS0,115200n8 noinitrd rw ip=dhcp
root=/dev/nfs
nfsroot=192.168.1.55:/home/filesys,nolock mem=100M
v4l2_video_capture=:device=TVP5146
video=dm64xxfb:output=ntsc
文件系统：NFS，文件系统的路径：nfsroot=192.168.1.55:/home/filesys；IP:DHCP；输入：数字CMOS输入；输出PAL
setenv bootargs console=ttyS0,115200n8 noinitrd rw ip=dhcp
root=/dev/nfs
nfsroot=192.168.1.55:/home/filesys,nolock mem=100M
v4l2_video_capture=:device=MT9T001
video=dm64xxfb:output=pal
文件系统：本地FLASH；IP:固定IP；输入：数字CMOS输入；输出PAL
setenv bootargs console=ttyS0,115200n8 noinitrd rw
rootfstype=yaffs2
ip=192.168.1.11:192.168.1.55:192.168.1.1:255.255.255.0:192.168.1.11::off
root=/dev/mtdblock3 nolock
mem=90M v4l2_video_capture=:device=MT9T001
video=dm64xxfb:output=pal
DM6446:
文件系统：NFS，文件系统的路径：nfsroot=192.168.1.55:/home/filesys；IP:DHCP；输入：模拟输入；输出PAL
setenv bootargs console=ttyS0,115200n8 noinitrd rw ip=dhcp
root=/dev/nfs
nfsroot=192.168.1.55:/home/filesys,nolock mem=38M
v4l2_video_capture=:device=TVP5146
video=dm64xxfb:output=pal
文件系统：本地硬盘；IP:DHCP；输入：模拟输入；输出PAL
setenv bootargs console=ttyS0,115200n8 noinitrd rw ip=dhcp
root=/dev/hda1
nfsroot=192.168.1.55:/home/filesys,nolock mem=38M
v4l2_video_capture=:device=TVP5146
video=dm64xxfb:output=pal
文件系统：NFS，文件系统的路径：nfsroot=192.168.1.55:/home/filesys；IP:固定IP；输入：模拟输入；输出NTSC
setenv bootargs console=ttyS0,115200n8 noinitrd rw
ip=192.168.1.240::192.168.1.2 root=/dev/nfs
nfsroot=192.168.1.55:/home/filesys, nolock mem=38M
video=dm64xxfb:output=ntsc v4l2_video_capture=:device=TVP5146
文件系统：本地硬盘；IP:固定IP；输入：模拟输入；输出PAL
setenv bootargs console=ttyS0,115200n8 noinitrd rw
ip=192.168.1.240::192.168.1.2 root=/dev/hda1
nfsroot=192.168.1.55:/home/filesys,nolock mem=38M
v4l2_video_capture=:device=TVP5146
video=dm64xxfb:output=pal
烧录内核至FLASH
DM355:
tftp 80700000 uImage-dm355:其中uImage-dm355为对应的文件名
nand erase 400000 200000
nand write 0x80700000 0x400000 0x200000
setenv bootcmd 'nboot 0x80700000 0 0x400000;bootm'
DM6446
tftp
erase 0x2040000
+0x157fb0(其中0x157fb0为对应内核文件的大小，通过tftp命令可以统计出来)
setenv bootcmd 'bootm 0x2040000'
cp.b 0x80700000 0x2040000
0x157fb0(其中0x157fb0为对应内核文件的大小，通过tftp命令可以统计出来)
LINUX 常用命令
路径切换命令：
显示当前所在目录路径
pwd
进入/root/encode目录
cd /root/encode
如果目前所在目录是/root
则输入：
cd encode即可进入/root/encode目录
驱动挂载命令：
查看系统上挂载的移动设备
fdisk -l
将USB设备（/dev/sda1）mount到mnt/usb目录下
mount /dev/sda1 /mnt/usb
拷贝命令：
从目录A(/root/encode)拷贝一文件到目录B(mnt/usb)
cp /root/encode/test.mpeg4 mnt/usb
进程终止命令
显示系统进程：ps -a
终止某进程： kill 996(996为目前某进程的PID号）
应用程序执行命令
执行应用程序encode
./encode
后台执行应用程序encode
./encode&(在DM355脱机方式，建议通过此方式执行应用程序，方可以通过kill命令进行进程的终止)
打包命令
tar -zcf A.tar.gz B（其中B为欲打包的目录，A为压缩包的命名）
解包命令
tar -xzf ti-davinci.tar.gz（其中
ti-davinci.tar.gz欲解包的命名，解压在当前目录
DM355 DVEVM软件安装
安装会有以下三种提示符：
1.host $ 主机命令SHELL窗口提示符
2.EVM # 输入命令到 U-Boot shell窗口，通过串口与目标板通信
3.target $输入命令到 Linux shell窗口，通过串口与目标板通信
一.
COPY以下文件到电脑上一个tmp临时目录下,需1.2G空间以上
❏ mvl_4_0_1_demo_sys_setuplinux.bin
❏ mvl_4_0_1_demo_target_setuplinux.bin
❏ lsp_DM355_setuplinux_#_##_##_##.bin
❏ dvsdk_DM355_setuplinux_#_##_##_##.bin
❏ xdc_setuplinux_#_##_##_##.bin
确保有一个X graphical display，可通过DISPLAY环境变量来设置
csh:
host $ setenv DISPLAY cnabc0314159d1:0
ksh or bash:
host $ export DISPLAY=cnabc0314159d1:0
二.
正式安装
1.以ROOT身份登录LINUX主机，这样可运行X graphical installer还安装MontaVista
Linux.
进入以上的tmp下执行以下命令：
host $ ./mvl_4_0_1_demo_sys_setuplinux.bin
host $ ./mvl_4_0_1_demo_target_setuplinux.bin
host $ ./lsp_DM355_setuplinux_#_##_##_##.bin
以上可能需花几分钟
（注：若不能执行可运行chmod +x *.bin，更改文件属性为可执行文件）
建议不要安装在默认目录，如可选/opt/mv_pro_4.0.1
执行以上命令后在/opt/_4.mv_pro0.1下出现以下三个文件
■ mvltools4.0.1-no-target.tar.gz
■ mvl4.0.1-target_path.tar.gz
■ DaVinciLSP-#_#_#_#.tar.gz
三.
进入/opt/_4.mv_pro0.1执行：
host $ cd /opt/mv_pro_4.0.1
而后用以下命令解压缩
host $ tar zxf mvltools4.0.1-no-target.tar.gz
host $ tar zxf mvl4.0.1-target_path.tar.gz
host $ tar zxf DaVinciLSP-#_#_#_#.tar.gz
以上会创建以下目录
/opt/mv_pro_4.0.1/montavista/ directory
四.安装DVSDK software
DVSDK software包括 Codec Engine components, sample data files, xDAIS
and xDM header files, and a contiguous memory allocator for Linux (CMEM).
以USER帐号登录,以下参考用户家(HOME)目录"~"
host $ cd /tmp(进入最开始临时目录)
host $ ./dvsdk_DM355_setuplinux_#_##_##_##.bin
不要安装在默认目录下,安装在USER家目录下,如/home/<useracct>
host $ cd /tmp
host $ ./xdc_setuplinux_#_##_##_##.bin
到此为止,可以删除COPY到TMP下的文件了.
注:可用rm -rf来移除以上所安装元件.
五.安装AV 数据光盘
host $ cd ~/dvsdk_1_xx
host $ cp /mnt/cdrom/data.tar.gz . (注: 点.表示当前目录)
host $ tar xfz data.tar.gz
六.按NFS (NETWORK FILE SYYSTEM)
1.以USER 进入
host $ cd ~
host $ mkdir -p workdir/filesys
host $ cd workdir/filesys
2.切换到root
host $ su root
3.进入之前安装目录 （useracct: user account,用户帐号名称）
host $ cp -a
/opt/mv_pro_4.U0.1/montavista/pro/devkit/arm/v5t_le/target/* .
host $ chown -R <useracct> opt （改变属性）
4.编辑/etc/exports输出文件，在文件系统区域加入以下行：（不要用~，用全路径）
/home/<useracct>/workdir/filesys *(rw,no_root_squash,no_all_squash,sync)
5.仍然是ROOT ，用下命令让NFS SERVER知道配置的改变及启动一NFS restart.
host $ /usr/sbin/exportfs -a
host $ /sbin/service nfs restart
注：可以用-ra 重新输出所有目录。
七.测试NFS SETUP
1.取得主机IP地址
host $ /sbin/ifconfig
2.打开一个RS232终端窗口(WINDOW 下用HyperTerminal,LINUX下用Minicom)
3.打开EVM电源,不要自动引导,设置以下变量:
EVM # setenv nfshost <ip address of nfs host>
EVM # setenv rootpath <directory to mount>
EVM # setenv bootargs console=ttyS0,115200n8 \
noinitrd rw ip=dhcp root=/dev/nfs \
nfsroot=$(nfshost):$(rootpath),nolock mem=116M
此directory to
mount必须是以上步骤六.4中的目录,如/home/<useracct>/workdir/filesys
4.保存变量,就不用每次EVM上电时重新设置
EVM # saveenv
5.用NFS 来BOOT EVM
EVM # boot
6.设置BOOT时的视频制式PAL/NTSC
设置J1跳线，即设置U-BOOT下的Videostd 环境变量
八.设置bootargs,bootcmd给核心，以及VPBE用
bootargs=`console=ttyS0,115200n8 ip=dhcp \
root=/dev/mtdblock3 rw rootfstype=yaffs2 mem=116M`
bootcmd=`setenv setboot setenv bootargs \$(bootargs) \
video=dm64xxfb:output=\$(videostd);run setboot;bootm \
0x80700000`
以上为NTSC，PAL需修改
九.安装DM355
DVSDK时会有以下附件,但只是DEMO版,若要正式产品可到http://www.ti.com/dvevmupdates
下式带正版授权的版本
❏ Sequential JPEG Decoder
❏ JPEG Sequential Encoder
❏ MPEG4 Restricted Simple Profile Decoder
❏ MPEG4 Simple Profile Encoder
十.设置BUILD及开发环境
以USER帐号进入NFS 文件系统,设置PATH变量,以便MontaVista tool chain host
tools and cross
compiler (arm_v5t_le-gcc)可以找到,比如对于MontaVista
LSP,如是安装在上面的/opt/mv_pro_4.0.1下(默认）则需在SHELL RESOURCE
FILE下（如~/.bashrc）增加一定义就可，如不在默认目录，则~/.bashrc中修改：
PATH="/opt/mv_pro_4.0.1/montavista/pro/devkit/arm/v5t_le/bin:
/opt/mv_pro_4.0.1/montavista/pro/bin:
/opt/mv_pro_4.0.1/montavista/common/bin:$PATH"
修改后用以下命令使其在当前环境下即时起作用
host $ source .bashrc
十一.当有输出NFS文件系统及建立以下环境后,就可以实现一简单例子了
以USER进入NFS主机系统,执行以下
1) host $ mkdir ~/workdir/filesys/opt/hello
2) host $ cd ~/workdir/filesys/opt/hello
3）创建hello.c文件
#include <stdio.h>
int main() {
printf("Buongiorno DaVinci!\n");
return 0;
}
4）host $ arm_v5t_le-gcc hello.c -o hello
进入目标板系统（如上面建立的串口通信），执行以下
1) target $ cd /opt/hello
2) Run ./hello. The output should be:
Buongiorno DaVinci!
十二. BUILD构建一新的LINUX内核
如果有修改LINUX内核源码,则需重新BUILD内核,而后再启动,可以直接覆盖原来NAND
FLASH中的,或以U-BOOT方式,用TFTP连接到网络来启动.
需确保在你的路径中有以下工具
PATH="/opt/mv_pro_4.0.1/montavista/pro/devkit/arm/v5t_le/bin:
/opt/mv_pro_4.0.1/montavista/pro/bin:$PATH"
REBUILD LINUX内核
1.user进入
2.在家目录下建一MontaVista Linux Support Package (LSP)工作目录,COPY
embedded Linux 2.6.10 kernel及DaVinci drivers到此目录
host $ cd ~
host $ mkdir -p workdir/lsp
host $ cd workdir/lsp
host $ cp -R /opt/mv_pro_4.0.1/montavista/pro/devkit/lsp/ti-davinci .
3.配置内核
host $ cd ti-davinci
host $ make ARCH=arm CROSS_COMPILE=arm_v5t_le-
davinci_dm355_evm_defconfig
变量CROSS_COMPLIE用来定义一可执行的前缀(在编译期间)
修改内核时,可能要用到make menuconfig'命令，可参考MontaVista文档。
4.能动内核默认选项：
host $ make ARCH=arm CROSS_COMPILE=arm_v5t_le- checksetconfig
5.编绎内核：
host $ make ARCH=arm CROSS_COMPILE=arm_v5t_le- uImage
6。COPY UIMAGE-DM355到一目录，此目录可以U-Boot can use TFTP to download
it to the EVM.
host $ cp ~/workdir/lsp/ti_davinci/arch/arm/boot/uImage
/tftpboot/uImage-dm355
host $ chmod a+r /tftpboot/uImage-dm355
十三。重建DVEVM软件。
1.CD ~/dvsdk_#_##.
2.EDIT ~/dvsdk_#_##/Rules.make file
DVSDK_INSTALL_DIR=/home/<useracct>/dvsdk_#_##
EXEC_DIR=/home/<useracct>/workdir/filesys/opt/dvsdk
LINUXKERNEL_INSTALL_DIR=/home/<useracct>/workdir/lsp/ti-davinci
3.host $ make
host $ make install
十四。启动新的内核
1.打开EVM电源，不要自动BOOT
EVM # setenv bootcmd 'dhcp;bootm'
EVM # setenv serverip <tftp server ip address>
EVM # setenv bootfile uImage-dm355
EVM # setenv bootargs 'mem=116M console=ttyS0,115200n8
root=/dev/mtdblock3 rw rootfstype=yaffs2 ip=dhcp'
测试TFTP server有否安装
host $ rpm -q tftp-server
如没有，则安装TFTP
host $ rpm -ivh /db/ztree/useracct/tftp-server-#.##-#.rpm
测试TFTP安装否，用以下命令
host $ /sbin/chkconfig --list | grep tftp
打开TFTP
/sbin/chkconfig tftp on
注：The default root location for servicing TFTP files is /tftpboot
加载CMEM and accelerator kernel modules.
Target $ ./loadmodules.sh
运行：
Target $ ./encodedecode [options]
Options:
❏ -r | --resolution
Resolution of demo. Specify width x height. For example: -r 720x480
❏ -t | --time
Number of seconds to run the demo. By default, there is no time limit.
❏ -i | --interface
If used, causes the main demo interface to launch when this demo
exits. By default, this is off.
❏ -b | --bitrate
Specify the bit rate at which video should be encoded.
❏ -x
Select S-Video input format.
❏ -h | --help
Print this help message.
附录 A
**启动方式：
❏ TFTP boot with NAND flash file system (Section A.3.2)
❏ Flash boot with NFS file system (Section A.3.3)
❏ TFTP boot with NFS file system (Section A.3.4)
1.不以自动BOOT方式进入
2.按下列方式设置以下变量
3.保存 EVM # saveenv
4.启动 EVM # boot
* Booting from Flash Using Board's NAND Flash File System
EVM # setenv bootcmd 'nboot 0x80700000 0 0x400000;bootm'
EVM # setenv bootargs 'console=ttyS0,115200n8 ip=dhcp
root=/dev/mtdblock3 rw rootfstype=yaffs2 mem=116M'
* Booting via TFTP Using Board's NAND Flash File System
EVM # setenv bootcmd 'dhcp;bootm'
EVM # setenv bootargs 'mem=116M console=ttyS0,115200n8
root=/dev/mtdblock3 rw rootfstype=yaffs2 ip=dhcp'
EVM # setenv serverip <tftp server ip address>
EVM # setenv bootfile uImage-dm355
* Booting from Flash Using NFS File System
EVM # setenv bootcmd 'nboot 0x80700000 0 0x400000;bootm'
EVM # setenv nfshost <ip addr of nfs host>
EVM # setenv rootpath <directory to mount>
EVM # setenv bootargs 'console=ttyS0,115200n8 noinitrd rw
ip=dhcp root=/dev/nfs
nfsroot=$(nfshost):$(rootpath),nolock mem=116M'
* Booting via TFTP Using NFS File System
EVM # setenv bootcmd 'dhcp;bootm'
EVM # setenv serverip <ip addr of tftp server>
EVM # setenv bootfile <name of kernel image>
EVM # setenv rootpath <root directory to mount>
EVM # setenv nfshost <ip addr of nfs host>
EVM # setenv bootargs 'console=ttyS0,115200n8 noinitrd rw
ip=dhcp root=/dev/nfs nfsroot=$(nfshost):$(rootpath),nolock
mem=116M'
**Updating/Restoring the Bootloaders
BOOT过程
EVM board RESET后 ROM bootloader (RBL)运行，初始化板及从NAND flash
memory加载UBL (User Bootloader)到内存，接着UBL从NAND flash
memory加载U-Boot bootloader，U-Boot bootloader负责加载及启动LINUX 内核。
因此有两个IMGAE（映像）储存在NAND FLASH：UBL and U-Boot
如果U-BOOT在FLASH中未动过，可用它自已更新，如工作的U-Boot (or UBL)
images不在FLASH，可用CCSUDIO及emulator.恢复。
在DVSDK的安装目录下有UBL, U-Boot, and the NAND
programmer，典型位置是/home/<useracct>/dvsdk_#_##/PSP_#_#_#_#/board_utilities.
升级Updating U-Boot Using U-Boot
1.分配静态IP 给EVM BOARD ：EVM # setenv ipaddr <static IP address>
分配动态IP ：EVM # dhcp
EVM # setenv ipaddr <IP address returned by
dhcp>
2.TFTP SERVER IP ：EVM # setenv serverip <TFTP server IP address>
3.保存EVM # saveenv
4.Load
U-Boot。需指定内核文件名（通常在/TFTP下）及目的地址（DDR），可任意选择
EVM # tftp 80800000 <u-boot file name>
如操作成功，有以下信息
EVM # tftp 80800000 u-boot-1.2.0-dm355_evm.bin
TFTP from server <IP addr>; our IP address is <IP addr>
Filename 'u-boot-1.2.0-dm355_evm.bin'.
Load address: 0x80800000
Loading: #########################
done
Bytes transferred = 127340 (1f16c hex)
5.撺除以前的U-BOOT（位于0x00200000）
EVM # nand erase 180000 20000
6.写新U-BOOT
EVM # nand write 80800000 180000 20000
7.EVM RESET后,可以通过串口终端显示U-BOOT是否成功工作。
** Updating UBL and U-Boot Bootloaders Using an Emulator and CCStudio
如UBL and U-Boot 不在FLASH中,则需用CCSUDIO及仿真器加载
1.提取NAND programmer
utilities,在DVSDK安装目录下,一般为/home/<useracct>/dvsdk_#_##/PSP_#_#_#_#/board_utilities.放到PC上,此PC要装有CCSUDIO3.3以上及
XDS560 or XDS510 emulator.
2.设置 CCStudio以连接到板上,用CCStudio Setup and the DM355 GEL files设置
3.连接emulator到板上,开EVM电源
4.开启CCStudio and connect to the device (Alt+C).
5.program NAND_programmer.out and run it (F5).
6. Enter the UBL path name and file name (ublDM355-nand.bin) in the
dialog box.
7.Enter the U-Boot path name and file name (uboot-1.2.0-dm355.bin)
in the dialog box.
8.Cycle power on the EVM board and press any key on the EVM's
monitor window to get the U-Boot prompt
**Restoring the NAND Flash Using NFS
恢复DVSDK NAND flash memory内容,包括内核及文件系统各demo application
software.
DVSDK NAND image文件在DVSDK CD中有,为"dm355_flash_image_#_##_##_##.tar"
Linux kernel (uImage-dm355)通常在/tftp下,通过TFTP加载
1.分配静态IP 给EVM BOARD ：EVM # setenv ipaddr <static IP address>
分配动态IP ：EVM # dhcp
EVM # setenv ipaddr <IP address returned by
dhcp>
2.加载内核IMAGE
EVM # tftp 80700000 uImage-dm355
EVM # nand erase 400000 200000
EVM # nand write 0x80700000 0x400000 0x200000
3.用NFS移值YAFFS2 image(dm355_flash_image_#_##_##_##.tar), YAFFS2
image在NFS Server root directory旁边
1)COPY dm355_flash_image_#_##_##_##.tar到NFS mounted root
directory(通常为/home/<useracct>/workdir/filesys)
2)EVM # setenv bootcmd 'nboot 0x80700000 0 0x400000; bootm'
EVM # setenv bootargs 'console=ttyS0,115200n8 noinitrd
ip=dhcp root=/dev/nfs rw nfsroot=<nfs_host_ip>:<nfs_root_path> mem=116M'
注:以上变量不需保存,因为NFS只是一个临时文件系统
3）用BOOT启动内核
4）EVM # mkdir /mnt/nand
EVM # flash_eraseall /dev/mtd3
EVM # mount -t yaffs2 /dev/mtdblock3 /mnt/nand/
EVM # cd /mnt/nand
EVM # tar xf /dm355_flash_image_#_##_##_##.tar
EVM # cd
EVM # umount /mnt/nand
EVM # reboot
1.host $ 主机命令SHELL窗口提示符
2.EVM # 输入命令到 U-Boot shell窗口，通过串口与目标板通信
3.target $输入命令到 Linux shell窗口，通过串口与目标板通信
一.
COPY以下文件到电脑上一个tmp临时目录下,需1.2G空间以上
❏ mvl_4_0_1_demo_sys_setuplinux.bin
❏ mvl_4_0_1_demo_target_setuplinux.bin
❏ lsp_DM355_setuplinux_#_##_##_##.bin
❏ dvsdk_DM355_setuplinux_#_##_##_##.bin
❏ xdc_setuplinux_#_##_##_##.bin
确保有一个X graphical display，可通过DISPLAY环境变量来设置
csh:
host $ setenv DISPLAY cnabc0314159d1:0
ksh or bash:
host $ export DISPLAY=cnabc0314159d1:0
二.
正式安装
1.以ROOT身份登录LINUX主机，这样可运行X graphical installer还安装MontaVista
Linux.
进入以上的tmp下执行以下命令：
host $ ./mvl_4_0_1_demo_sys_setuplinux.bin
host $ ./mvl_4_0_1_demo_target_setuplinux.bin
host $ ./lsp_DM355_setuplinux_#_##_##_##.bin
以上可能需花几分钟
（注：若不能执行可运行chmod +x *.bin，更改文件属性为可执行文件）
建议不要安装在默认目录，如可选/opt/mv_pro_4.0.1
执行以上命令后在/opt/_4.mv_pro0.1下出现以下三个文件
■ mvltools4.0.1-no-target.tar.gz
■ mvl4.0.1-target_path.tar.gz
■ DaVinciLSP-#_#_#_#.tar.gz
三.
进入/opt/_4.mv_pro0.1执行：
host $ cd /opt/mv_pro_4.0.1
而后用以下命令解压缩
host $ tar zxf mvltools4.0.1-no-target.tar.gz
host $ tar zxf mvl4.0.1-target_path.tar.gz
host $ tar zxf DaVinciLSP-#_#_#_#.tar.gz
以上会创建以下目录
/opt/mv_pro_4.0.1/montavista/ directory
四.安装DVSDK software
DVSDK software包括 Codec Engine components, sample data files, xDAIS
and xDM header files, and a contiguous memory allocator for Linux (CMEM).
以USER帐号登录,以下参考用户家(HOME)目录"~"
host $ cd /tmp(进入最开始临时目录)
host $ ./dvsdk_DM355_setuplinux_#_##_##_##.bin
不要安装在默认目录下,安装在USER家目录下,如/home/<useracct>
host $ cd /tmp
host $ ./xdc_setuplinux_#_##_##_##.bin
到此为止,可以删除COPY到TMP下的文件了.
注:可用rm -rf来移除以上所安装元件.
五.安装AV 数据光盘
host $ cd ~/dvsdk_1_xx
host $ cp /mnt/cdrom/data.tar.gz . (注: 点.表示当前目录)
host $ tar xfz data.tar.gz
六.按NFS (NETWORK FILE SYYSTEM)
1.以USER 进入
host $ cd ~
host $ mkdir -p workdir/filesys
host $ cd workdir/filesys
2.切换到root
host $ su root
3.进入之前安装目录 （useracct: user account,用户帐号名称）
host $ cp -a
/opt/mv_pro_4.U0.1/montavista/pro/devkit/arm/v5t_le/target/* .
host $ chown -R <useracct> opt （改变属性）
4.编辑/etc/exports输出文件，在文件系统区域加入以下行：（不要用~，用全路径）
/home/<useracct>/workdir/filesys *(rw,no_root_squash,no_all_squash,sync)
5.仍然是ROOT ，用下命令让NFS SERVER知道配置的改变及启动一NFS restart.
host $ /usr/sbin/exportfs -a
host $ /sbin/service nfs restart
注：可以用-ra 重新输出所有目录。
七.测试NFS SETUP
1.取得主机IP地址
host $ /sbin/ifconfig
2.打开一个RS232终端窗口(WINDOW 下用HyperTerminal,LINUX下用Minicom)
3.打开EVM电源,不要自动引导,设置以下变量:
EVM # setenv nfshost <ip address of nfs host>
EVM # setenv rootpath <directory to mount>
EVM # setenv bootargs console=ttyS0,115200n8 \
noinitrd rw ip=dhcp root=/dev/nfs \
nfsroot=$(nfshost):$(rootpath),nolock mem=116M
此directory to
mount必须是以上步骤六.4中的目录,如/home/<useracct>/workdir/filesys
4.保存变量,就不用每次EVM上电时重新设置
EVM # saveenv
5.用NFS 来BOOT EVM
EVM # boot
6.设置BOOT时的视频制式PAL/NTSC
设置J1跳线，即设置U-BOOT下的Videostd 环境变量
八.设置bootargs,bootcmd给核心，以及VPBE用
bootargs=`console=ttyS0,115200n8 ip=dhcp \
root=/dev/mtdblock3 rw rootfstype=yaffs2 mem=116M`
bootcmd=`setenv setboot setenv bootargs \$(bootargs) \
video=dm64xxfb:output=\$(videostd);run setboot;bootm \
0x80700000`
以上为NTSC，PAL需修改
九.安装DM355
DVSDK时会有以下附件,但只是DEMO版,若要正式产品可到http://www.ti.com/dvevmupdates
下式带正版授权的版本
❏ Sequential JPEG Decoder
❏ JPEG Sequential Encoder
❏ MPEG4 Restricted Simple Profile Decoder
❏ MPEG4 Simple Profile Encoder
十.设置BUILD及开发环境
以USER帐号进入NFS 文件系统,设置PATH变量,以便MontaVista tool chain host
tools and cross
compiler (arm_v5t_le-gcc)可以找到,比如对于MontaVista
LSP,如是安装在上面的/opt/mv_pro_4.0.1下(默认）则需在SHELL RESOURCE
FILE下（如~/.bashrc）增加一定义就可，如不在默认目录，则~/.bashrc中修改：
PATH="/opt/mv_pro_4.0.1/montavista/pro/devkit/arm/v5t_le/bin:
/opt/mv_pro_4.0.1/montavista/pro/bin:
/opt/mv_pro_4.0.1/montavista/common/bin:$PATH"
修改后用以下命令使其在当前环境下即时起作用
host $ source .bashrc
十一.当有输出NFS文件系统及建立以下环境后,就可以实现一简单例子了
以USER进入NFS主机系统,执行以下
1) host $ mkdir ~/workdir/filesys/opt/hello
2) host $ cd ~/workdir/filesys/opt/hello
3）创建hello.c文件
#include <stdio.h>
int main() {
printf("Buongiorno DaVinci!\n");
return 0;
}
4）host $ arm_v5t_le-gcc hello.c -o hello
进入目标板系统（如上面建立的串口通信），执行以下
1) target $ cd /opt/hello
2) Run ./hello. The output should be:
Buongiorno DaVinci!
十二. BUILD构建一新的LINUX内核
如果有修改LINUX内核源码,则需重新BUILD内核,而后再启动,可以直接覆盖原来NAND
FLASH中的,或以U-BOOT方式,用TFTP连接到网络来启动.
需确保在你的路径中有以下工具
PATH="/opt/mv_pro_4.0.1/montavista/pro/devkit/arm/v5t_le/bin:
/opt/mv_pro_4.0.1/montavista/pro/bin:$PATH"
REBUILD LINUX内核
1.user进入
2.在家目录下建一MontaVista Linux Support Package (LSP)工作目录,COPY
embedded Linux 2.6.10 kernel及DaVinci drivers到此目录
host $ cd ~
host $ mkdir -p workdir/lsp
host $ cd workdir/lsp
host $ cp -R /opt/mv_pro_4.0.1/montavista/pro/devkit/lsp/ti-davinci .
3.配置内核
host $ cd ti-davinci
host $ make ARCH=arm CROSS_COMPILE=arm_v5t_le-
davinci_dm355_evm_defconfig
变量CROSS_COMPLIE用来定义一可执行的前缀(在编译期间)
修改内核时,可能要用到make menuconfig'命令，可参考MontaVista文档。
4.能动内核默认选项：
host $ make ARCH=arm CROSS_COMPILE=arm_v5t_le- checksetconfig
5.编绎内核：
host $ make ARCH=arm CROSS_COMPILE=arm_v5t_le- uImage
6。COPY UIMAGE-DM355到一目录，此目录可以U-Boot can use TFTP to download
it to the EVM.
host $ cp ~/workdir/lsp/ti_davinci/arch/arm/boot/uImage
/tftpboot/uImage-dm355
host $ chmod a+r /tftpboot/uImage-dm355
十三。重建DVEVM软件。
1.CD ~/dvsdk_#_##.
2.EDIT ~/dvsdk_#_##/Rules.make file
DVSDK_INSTALL_DIR=/home/<useracct>/dvsdk_#_##
EXEC_DIR=/home/<useracct>/workdir/filesys/opt/dvsdk
LINUXKERNEL_INSTALL_DIR=/home/<useracct>/workdir/lsp/ti-davinci
3.host $ make
host $ make install
十四。启动新的内核
1.打开EVM电源，不要自动BOOT
EVM # setenv bootcmd 'dhcp;bootm'
EVM # setenv serverip <tftp server ip address>
EVM # setenv bootfile uImage-dm355
EVM # setenv bootargs 'mem=116M console=ttyS0,115200n8
root=/dev/mtdblock3 rw rootfstype=yaffs2 ip=dhcp'
测试TFTP server有否安装
host $ rpm -q tftp-server
如没有，则安装TFTP
host $ rpm -ivh /db/ztree/useracct/tftp-server-#.##-#.rpm
测试TFTP安装否，用以下命令
host $ /sbin/chkconfig --list | grep tftp
打开TFTP
/sbin/chkconfig tftp on
注：The default root location for servicing TFTP files is /tftpboot
加载CMEM and accelerator kernel modules.
Target $ ./loadmodules.sh
运行：
Target $ ./encodedecode [options]
Options:
❏ -r | --resolution
Resolution of demo. Specify width x height. For example: -r 720x480
❏ -t | --time
Number of seconds to run the demo. By default, there is no time limit.
❏ -i | --interface
If used, causes the main demo interface to launch when this demo
exits. By default, this is off.
❏ -b | --bitrate
Specify the bit rate at which video should be encoded.
❏ -x
Select S-Video input format.
❏ -h | --help
Print this help message.
附录 A
**启动方式：
❏ TFTP boot with NAND flash file system (Section A.3.2)
❏ Flash boot with NFS file system (Section A.3.3)
❏ TFTP boot with NFS file system (Section A.3.4)
1.不以自动BOOT方式进入
2.按下列方式设置以下变量
3.保存 EVM # saveenv
4.启动 EVM # boot
* Booting from Flash Using Board's NAND Flash File System
EVM # setenv bootcmd 'nboot 0x80700000 0 0x400000;bootm'
EVM # setenv bootargs 'console=ttyS0,115200n8 ip=dhcp
root=/dev/mtdblock3 rw rootfstype=yaffs2 mem=116M'
* Booting via TFTP Using Board's NAND Flash File System
EVM # setenv bootcmd 'dhcp;bootm'
EVM # setenv bootargs 'mem=116M console=ttyS0,115200n8
root=/dev/mtdblock3 rw rootfstype=yaffs2 ip=dhcp'
EVM # setenv serverip <tftp server ip address>
EVM # setenv bootfile uImage-dm355
* Booting from Flash Using NFS File System
EVM # setenv bootcmd 'nboot 0x80700000 0 0x400000;bootm'
EVM # setenv nfshost <ip addr of nfs host>
EVM # setenv rootpath <directory to mount>
EVM # setenv bootargs 'console=ttyS0,115200n8 noinitrd rw
ip=dhcp root=/dev/nfs
nfsroot=$(nfshost):$(rootpath),nolock mem=116M'
* Booting via TFTP Using NFS File System
EVM # setenv bootcmd 'dhcp;bootm'
EVM # setenv serverip <ip addr of tftp server>
EVM # setenv bootfile <name of kernel image>
EVM # setenv rootpath <root directory to mount>
EVM # setenv nfshost <ip addr of nfs host>
EVM # setenv bootargs 'console=ttyS0,115200n8 noinitrd rw
ip=dhcp root=/dev/nfs nfsroot=$(nfshost):$(rootpath),nolock
mem=116M'
**Updating/Restoring the Bootloaders
BOOT过程
EVM board RESET后 ROM bootloader (RBL)运行，初始化板及从NAND flash
memory加载UBL (User Bootloader)到内存，接着UBL从NAND flash
memory加载U-Boot bootloader，U-Boot bootloader负责加载及启动LINUX 内核。
因此有两个IMGAE（映像）储存在NAND FLASH：UBL and U-Boot
如果U-BOOT在FLASH中未动过，可用它自已更新，如工作的U-Boot (or UBL)
images不在FLASH，可用CCSUDIO及emulator.恢复。
在DVSDK的安装目录下有UBL, U-Boot, and the NAND
programmer，典型位置是/home/<useracct>/dvsdk_#_##/PSP_#_#_#_#/board_utilities.
升级Updating U-Boot Using U-Boot
1.分配静态IP 给EVM BOARD ：EVM # setenv ipaddr <static IP address>
分配动态IP ：EVM # dhcp
EVM # setenv ipaddr <IP address returned by
dhcp>
2.TFTP SERVER IP ：EVM # setenv serverip <TFTP server IP address>
3.保存EVM # saveenv
4.Load
U-Boot。需指定内核文件名（通常在/TFTP下）及目的地址（DDR），可任意选择
EVM # tftp 80800000 <u-boot file name>
如操作成功，有以下信息
EVM # tftp 80800000 u-boot-1.2.0-dm355_evm.bin
TFTP from server <IP addr>; our IP address is <IP addr>
Filename 'u-boot-1.2.0-dm355_evm.bin'.
Load address: 0x80800000
Loading: #########################
done
Bytes transferred = 127340 (1f16c hex)
5.撺除以前的U-BOOT（位于0x00200000）
EVM # nand erase 180000 20000
6.写新U-BOOT
EVM # nand write 80800000 180000 20000
7.EVM RESET后,可以通过串口终端显示U-BOOT是否成功工作。
** Updating UBL and U-Boot Bootloaders Using an Emulator and CCStudio
如UBL and U-Boot 不在FLASH中,则需用CCSUDIO及仿真器加载
1.提取NAND programmer
utilities,在DVSDK安装目录下,一般为/home/<useracct>/dvsdk_#_##/PSP_#_#_#_#/board_utilities.放到PC上,此PC要装有CCSUDIO3.3以上及
XDS560 or XDS510 emulator.
2.设置 CCStudio以连接到板上,用CCStudio Setup and the DM355 GEL files设置
3.连接emulator到板上,开EVM电源
4.开启CCStudio and connect to the device (Alt+C).
5.program NAND_programmer.out and run it (F5).
6. Enter the UBL path name and file name (ublDM355-nand.bin) in the
dialog box.
7.Enter the U-Boot path name and file name (uboot-1.2.0-dm355.bin)
in the dialog box.
8.Cycle power on the EVM board and press any key on the EVM's
monitor window to get the U-Boot prompt
**Restoring the NAND Flash Using NFS
恢复DVSDK NAND flash memory内容,包括内核及文件系统各demo application
software.
DVSDK NAND image文件在DVSDK CD中有,为"dm355_flash_image_#_##_##_##.tar"
Linux kernel (uImage-dm355)通常在/tftp下,通过TFTP加载
1.分配静态IP 给EVM BOARD ：EVM # setenv ipaddr <static IP address>
分配动态IP ：EVM # dhcp
EVM # setenv ipaddr <IP address returned by
dhcp>
2.加载内核IMAGE
EVM # tftp 80700000 uImage-dm355
EVM # nand erase 400000 200000
EVM # nand write 0x80700000 0x400000 0x200000
3.用NFS移值YAFFS2 image(dm355_flash_image_#_##_##_##.tar), YAFFS2
image在NFS Server root directory旁边
1)COPY dm355_flash_image_#_##_##_##.tar到NFS mounted root
directory(通常为/home/<useracct>/workdir/filesys)
2)EVM # setenv bootcmd 'nboot 0x80700000 0 0x400000; bootm'
EVM # setenv bootargs 'console=ttyS0,115200n8 noinitrd
ip=dhcp root=/dev/nfs rw nfsroot=<nfs_host_ip>:<nfs_root_path> mem=116M'
注:以上变量不需保存,因为NFS只是一个临时文件系统
3）用BOOT启动内核
4）EVM # mkdir /mnt/nand
EVM # flash_eraseall /dev/mtd3
EVM # mount -t yaffs2 /dev/mtdblock3 /mnt/nand/
EVM # cd /mnt/nand
EVM # tar xf /dm355_flash_image_#_##_##_##.tar
EVM # cd
EVM # umount /mnt/nand
EVM # reboot
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